From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18DB3C32771 for ; Mon, 27 Jan 2020 08:55:58 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C897620702 for ; Mon, 27 Jan 2020 08:55:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TsaWa8ll" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C897620702 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:41778 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iw0BZ-0005WJ-07 for qemu-devel@archiver.kernel.org; Mon, 27 Jan 2020 03:55:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51997) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iw0Aq-0004hh-TM for qemu-devel@nongnu.org; Mon, 27 Jan 2020 03:55:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iw0Ao-0003T8-Fs for qemu-devel@nongnu.org; Mon, 27 Jan 2020 03:55:12 -0500 Received: from mail-qv1-xf41.google.com ([2607:f8b0:4864:20::f41]:42504) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iw0Ao-0003Sw-AK for qemu-devel@nongnu.org; Mon, 27 Jan 2020 03:55:10 -0500 Received: by mail-qv1-xf41.google.com with SMTP id dc14so4100798qvb.9 for ; Mon, 27 Jan 2020 00:55:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=NqDee+KM7MyUdml3onoslb1/X5F9cEJtYYQA7vXgqJE=; b=TsaWa8llTLbjPdXLmfC5msNphVymXFvciSp+qjuNnBeKw93mq02PxL5SAtzzlFFDNN o+4hmibJIe3QniRK5mgYSPPpnR+RAu3cr8puYPyoLvLDQH+qR07MT1nGwPVmMKyHhA4t cBWQUStQepln4dXur6/wNQbl7s939lw7KAs2AYGUQxIWH/e95zkqbHjBbDxd/87bfsvL dXcszaa7b03XXwcUAZBGRZxpZFN/VdXdxx5zikBgR1ZUWvotlPlC0v8Uxdo8OnB2PIX6 d8iIJywhxyLqFu6CkEZc9yXhqElYL+4r1SiPtIj0O6vmOj6fa3QPdfhDgNOJ//aNagjQ a7pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=NqDee+KM7MyUdml3onoslb1/X5F9cEJtYYQA7vXgqJE=; b=slWU/MSZkLMCvTEu/09+xlA3vg7M3UJVJTfZ/pEJx4HYK3m6wtPTsdW3eP0rc4Qibc qLEDaD3Ay8qaZ1mmeKm2aIWTGwXRkz4Ei+5Z9kshMcefGS6JtCpCezzgJeSYhsK8RAA/ Il5NZld1k2Gt1/sDwEcjSwzlvPxBn3xPx6kB2R6e0B5eJqeCUVCGD1hRSn+w7EYKzC6T VFgLiweF8YeRINMtKQnrE6L4is+Zy+9lVTK3TzbiwkIUOTZDwcClFFoP+n9/+ZHD66zU ugnvytcC+XrKYy+iar4mRGLPN6GLe1NTJdszz/KoRmD8N0bdpSW4koQkMOY4NRI7R2+H +r3g== X-Gm-Message-State: APjAAAUVQQv9m/3H7fxWhWyGC/+3vQxCx8fnFQWksuNBnW5ukPIOPfOa fR+TQffA52A/7k4lcBBDj9rnqpDy46m5LmtSXWs= X-Google-Smtp-Source: APXvYqyccws+iTMuD4BOeVI4cwh63aj6M64D6Tpgln8CXSc0ClEICdOEjvwqHYbp5awDLJVnInhOxYeNne+/rw/mkQk= X-Received: by 2002:a0c:8d0a:: with SMTP id r10mr14694895qvb.7.1580115309651; Mon, 27 Jan 2020 00:55:09 -0800 (PST) MIME-Version: 1.0 References: <1580079311-20447-1-git-send-email-aleksandar.markovic@rt-rk.com> <1580079311-20447-2-git-send-email-aleksandar.markovic@rt-rk.com> In-Reply-To: <1580079311-20447-2-git-send-email-aleksandar.markovic@rt-rk.com> From: Michael Rolnik Date: Mon, 27 Jan 2020 10:54:26 +0200 Message-ID: Subject: Re: [PATCH rc3 01/30] target/avr: Add basic parameters for new AVR platform To: Aleksandar Markovic Content-Type: multipart/alternative; boundary="000000000000bc6c9f059d1b43bd" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::f41 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sarah Harris , Richard Henderson , QEMU Developers , Aleksandar Markovic Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000bc6c9f059d1b43bd Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Thanks for you help guys. On Mon, Jan 27, 2020 at 12:55 AM Aleksandar Markovic < aleksandar.markovic@rt-rk.com> wrote: > From: Michael Rolnik > > This includes definitions of various basic parameters needed > for integration of a new platform into QEMU. > > Co-developed-by: Michael Rolnik > Co-developed-by: Sarah Harris > Signed-off-by: Michael Rolnik > Signed-off-by: Sarah Harris > Signed-off-by: Michael Rolnik > Acked-by: Igor Mammedov > Tested-by: Philippe Mathieu-Daud=C3=A9 > Signed-off-by: Richard Henderson > Signed-off-by: Aleksandar Markovic > --- > target/avr/cpu-param.h | 37 ++++++++++++++++++++++++++ > target/avr/cpu.h | 72 > ++++++++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 109 insertions(+) > create mode 100644 target/avr/cpu-param.h > create mode 100644 target/avr/cpu.h > > diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h > new file mode 100644 > index 0000000..0c29ce4 > --- /dev/null > +++ b/target/avr/cpu-param.h > @@ -0,0 +1,37 @@ > +/* > + * QEMU AVR CPU > + * > + * Copyright (c) 2019 Michael Rolnik > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * > + */ > + > +#ifndef AVR_CPU_PARAM_H > +#define AVR_CPU_PARAM_H > + > +#define TARGET_LONG_BITS 32 > +/* > + * TARGET_PAGE_BITS cannot be more than 8 bits because > + * 1. all IO registers occupy [0x0000 .. 0x00ff] address range, and the= y > + * should be implemented as a device and not memory > + * 2. SRAM starts at the address 0x0100 > + */ > +#define TARGET_PAGE_BITS 8 > +#define TARGET_PHYS_ADDR_SPACE_BITS 24 > +#define TARGET_VIRT_ADDR_SPACE_BITS 24 > +#define NB_MMU_MODES 2 > + > + > +#endif > diff --git a/target/avr/cpu.h b/target/avr/cpu.h > new file mode 100644 > index 0000000..d122611 > --- /dev/null > +++ b/target/avr/cpu.h > @@ -0,0 +1,72 @@ > +/* > + * QEMU AVR CPU > + * > + * Copyright (c) 2019 Michael Rolnik > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * > + */ > + > +#ifndef QEMU_AVR_CPU_H > +#define QEMU_AVR_CPU_H > + > +#include "cpu-qom.h" > +#include "exec/cpu-defs.h" > + > +#define TCG_GUEST_DEFAULT_MO 0 > +#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU > +#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX) > +#define CPU_RESOLVING_TYPE TYPE_AVR_CPU > + > +/* > + * AVR has two memory spaces, data & code. > + * e.g. both have 0 address > + * ST/LD instructions access data space > + * LPM/SPM and instruction fetching access code memory space > + */ > +#define MMU_CODE_IDX 0 > +#define MMU_DATA_IDX 1 > + > +#define EXCP_RESET 1 > +#define EXCP_INT(n) (EXCP_RESET + (n) + 1) > + > +/* Number of CPU registers */ > +#define NUMBER_OF_CPU_REGISTERS 32 > +/* Number of IO registers accessible by ld/st/in/out */ > +#define NUMBER_OF_IO_REGISTERS 64 > + > +/* > + * Offsets of AVR memory regions in host memory space. > + * > + * This is needed because the AVR has separate code and data address > + * spaces that both have start from zero but have to go somewhere in > + * host memory. > + * > + * It's also useful to know where some things are, like the IO registers= . > + */ > +/* Flash program memory */ > +#define OFFSET_CODE 0x00000000 > +/* CPU registers, IO registers, and SRAM */ > +#define OFFSET_DATA 0x00800000 > +/* CPU registers specifically, these are mapped at the start of data */ > +#define OFFSET_CPU_REGISTERS OFFSET_DATA > +/* > + * IO registers, including status register, stack pointer, and memory > + * mapped peripherals, mapped just after CPU registers > + */ > +#define OFFSET_IO_REGISTERS (OFFSET_DATA + NUMBER_OF_CPU_REGISTERS) > + > +#define EF_AVR_MACH 0x7F > + > +#endif /* !defined (QEMU_AVR_CPU_H) */ > -- > 2.7.4 > > --=20 Best Regards, Michael Rolnik --000000000000bc6c9f059d1b43bd Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Thanks for you help guys.

On Mon, Jan 27, 2020 at 12:55 AM = Aleksandar Markovic <al= eksandar.markovic@rt-rk.com> wrote:
From: Michael Rolnik <mrolnik@gmail.com>

This includes definitions of various basic parameters needed
for integration of a new platform into QEMU.

Co-developed-by: Michael Rolnik <mrolnik@gmail.com>
Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk>
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk>
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
---
=C2=A0target/avr/cpu-param.h | 37 ++++++++++++++++++++++++++
=C2=A0target/avr/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0| 72 +++++++++++++++++++++= +++++++++++++++++++++++++++++
=C2=A02 files changed, 109 insertions(+)
=C2=A0create mode 100644 target/avr/cpu-param.h
=C2=A0create mode 100644 target/avr/cpu.h

diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
new file mode 100644
index 0000000..0c29ce4
--- /dev/null
+++ b/target/avr/cpu-param.h
@@ -0,0 +1,37 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the GNU<= br> + * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html> + */
+
+#ifndef AVR_CPU_PARAM_H
+#define AVR_CPU_PARAM_H
+
+#define TARGET_LONG_BITS 32
+/*
+ * TARGET_PAGE_BITS cannot be more than 8 bits because
+ * 1.=C2=A0 all IO registers occupy [0x0000 .. 0x00ff] address range, and = they
+ *=C2=A0 =C2=A0 =C2=A0should be implemented as a device and not memory
+ * 2.=C2=A0 SRAM starts at the address 0x0100
+ */
+#define TARGET_PAGE_BITS 8
+#define TARGET_PHYS_ADDR_SPACE_BITS 24
+#define TARGET_VIRT_ADDR_SPACE_BITS 24
+#define NB_MMU_MODES 2
+
+
+#endif
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
new file mode 100644
index 0000000..d122611
--- /dev/null
+++ b/target/avr/cpu.h
@@ -0,0 +1,72 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the GNU<= br> + * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html> + */
+
+#ifndef QEMU_AVR_CPU_H
+#define QEMU_AVR_CPU_H
+
+#include "cpu-qom.h"
+#include "exec/cpu-defs.h"
+
+#define TCG_GUEST_DEFAULT_MO 0
+#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
+#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
+#define CPU_RESOLVING_TYPE TYPE_AVR_CPU
+
+/*
+ * AVR has two memory spaces, data & code.
+ * e.g. both have 0 address
+ * ST/LD instructions access data space
+ * LPM/SPM and instruction fetching access code memory space
+ */
+#define MMU_CODE_IDX 0
+#define MMU_DATA_IDX 1
+
+#define EXCP_RESET 1
+#define EXCP_INT(n) (EXCP_RESET + (n) + 1)
+
+/* Number of CPU registers */
+#define NUMBER_OF_CPU_REGISTERS 32
+/* Number of IO registers accessible by ld/st/in/out */
+#define NUMBER_OF_IO_REGISTERS 64
+
+/*
+ * Offsets of AVR memory regions in host memory space.
+ *
+ * This is needed because the AVR has separate code and data address
+ * spaces that both have start from zero but have to go somewhere in
+ * host memory.
+ *
+ * It's also useful to know where some things are, like the IO registe= rs.
+ */
+/* Flash program memory */
+#define OFFSET_CODE 0x00000000
+/* CPU registers, IO registers, and SRAM */
+#define OFFSET_DATA 0x00800000
+/* CPU registers specifically, these are mapped at the start of data */ +#define OFFSET_CPU_REGISTERS OFFSET_DATA
+/*
+ * IO registers, including status register, stack pointer, and memory
+ * mapped peripherals, mapped just after CPU registers
+ */
+#define OFFSET_IO_REGISTERS (OFFSET_DATA + NUMBER_OF_CPU_REGISTERS)
+
+#define EF_AVR_MACH 0x7F
+
+#endif /* !defined (QEMU_AVR_CPU_H) */
--
2.7.4



--
Best Regards,
Michael Rolnik
--000000000000bc6c9f059d1b43bd--