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Mon, 18 Apr 2022 22:27:21 -0700 (PDT) MIME-Version: 1.0 References: <20220415093727.15323-1-frank.chang@sifive.com> In-Reply-To: From: Anup Patel Date: Tue, 19 Apr 2022 10:57:09 +0530 Message-ID: Subject: Re: [PATCH] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values To: Alistair Francis Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=apatel@ventanamicro.com; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Frank Chang , Bin Meng , "qemu-devel@nongnu.org Developers" , Jim Shu , Palmer Dabbelt , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Apr 19, 2022 at 10:52 AM Alistair Francis wrote: > > On Fri, Apr 15, 2022 at 7:37 PM wrote: > > > > From: Frank Chang > > > > Allow user to set core's marchid, mvendorid, mipid CSRs through > > -cpu command line option. > > > > Signed-off-by: Frank Chang > > Reviewed-by: Jim Shu > > --- > > target/riscv/cpu.c | 4 ++++ > > target/riscv/cpu.h | 4 ++++ > > target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++---- > > 3 files changed, 42 insertions(+), 4 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index ddda4906ff..2eea0f9be7 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -786,6 +786,10 @@ static Property riscv_cpu_properties[] = { > > DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), > > DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), > > > > + DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), > > + DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, 0), > > + DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, 0), > > Should we have non-zero defaults here? To do that, we need mvendorid for QEMU RISC-V. The marchid and mipid can be based on the QEMU version number. Regards, Anup > > Alistair > > > + > > DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), > > DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), > > DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index c069fe85fa..3ab92deb4b 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -370,6 +370,10 @@ struct RISCVCPUConfig { > > bool ext_zve32f; > > bool ext_zve64f; > > > > + uint32_t mvendorid; > > + uint64_t marchid; > > + uint64_t mipid; > > + > > /* Vendor-specific custom extensions */ > > bool ext_XVentanaCondOps; > > > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 341c2e6f23..9a02038adb 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -603,6 +603,36 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno, > > return RISCV_EXCP_NONE; > > } > > > > +static RISCVException read_mvendorid(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + CPUState *cs = env_cpu(env); > > + RISCVCPU *cpu = RISCV_CPU(cs); > > + > > + *val = cpu->cfg.mvendorid; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException read_marchid(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + CPUState *cs = env_cpu(env); > > + RISCVCPU *cpu = RISCV_CPU(cs); > > + > > + *val = cpu->cfg.marchid; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException read_mipid(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + CPUState *cs = env_cpu(env); > > + RISCVCPU *cpu = RISCV_CPU(cs); > > + > > + *val = cpu->cfg.mipid; > > + return RISCV_EXCP_NONE; > > +} > > + > > static RISCVException read_mhartid(CPURISCVState *env, int csrno, > > target_ulong *val) > > { > > @@ -3098,10 +3128,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > > [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, > > > > /* Machine Information Registers */ > > - [CSR_MVENDORID] = { "mvendorid", any, read_zero }, > > - [CSR_MARCHID] = { "marchid", any, read_zero }, > > - [CSR_MIMPID] = { "mimpid", any, read_zero }, > > - [CSR_MHARTID] = { "mhartid", any, read_mhartid }, > > + [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid }, > > + [CSR_MARCHID] = { "marchid", any, read_marchid }, > > + [CSR_MIMPID] = { "mimpid", any, read_mipid }, > > + [CSR_MHARTID] = { "mhartid", any, read_mhartid }, > > > > /* Machine Trap Setup */ > > [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL, > > -- > > 2.35.1 > > > > >