From: Deepak Gupta <debug@rivosinc.com>
To: Alexey Baturo <baturo.alexey@gmail.com>
Cc: richard.henderson@linaro.org, zhiwei_liu@linux.alibaba.com,
palmer@dabbelt.com, Alistair.Francis@wdc.com,
sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: Re: [PATCH v3 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking
Date: Thu, 4 Jan 2024 16:46:29 -0800 [thread overview]
Message-ID: <CAKC1njQwWxwSeGKVMUtUVmTkWEO-Z8zL8O20VmC+NJvUQNj94w@mail.gmail.com> (raw)
In-Reply-To: <20240103185716.1790546-4-me@deliversmonkey.space>
On Wed, Jan 3, 2024 at 10:59 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
> +
> +bool riscv_cpu_bare_mode(CPURISCVState *env)
> +{
> + int satp_mode = 0;
> +#ifndef CONFIG_USER_ONLY
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> + satp_mode = get_field(env->satp, SATP32_MODE);
> + } else {
> + satp_mode = get_field(env->satp, SATP64_MODE);
> + }
> +#endif
> + return (satp_mode == VM_1_10_MBARE);
> +}
> +
Assume the CPU was in S or U with satp = non-bare mode but then a
transfer to M-mode happened.
In that case, even though the CPU is in M mode, the above function
will return non-bare mode and enforce
signed extension on M mode pointer masking (if enabled).
right or am I missing something here?
next prev parent reply other threads:[~2024-01-05 0:47 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-03 18:57 [PATCH v3 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
2024-01-03 18:57 ` [PATCH v3 1/6] target/riscv: Remove obsolete pointer masking extension code Alexey Baturo
2024-01-05 5:04 ` Alistair Francis
2024-01-05 7:23 ` Alexey Baturo
2024-01-03 18:57 ` [PATCH v3 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8 Alexey Baturo
2024-01-03 18:57 ` [PATCH v3 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking Alexey Baturo
2024-01-05 0:46 ` Deepak Gupta [this message]
2024-01-05 7:33 ` Alexey Baturo
2024-01-05 18:13 ` Deepak Gupta
2024-01-03 18:57 ` [PATCH v3 4/6] target/riscv: Add pointer masking tb flags Alexey Baturo
2024-01-03 22:08 ` Richard Henderson
2024-01-03 18:57 ` [PATCH v3 5/6] target/riscv: Update address modify functions to take into account pointer masking Alexey Baturo
2024-01-03 22:18 ` Richard Henderson
2024-01-05 1:02 ` Deepak Gupta
2024-01-05 7:29 ` Alexey Baturo
2024-01-05 18:07 ` Deepak Gupta
2024-01-03 18:57 ` [PATCH v3 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension Alexey Baturo
2024-01-05 5:27 ` Alistair Francis
2024-01-05 7:23 ` Alexey Baturo
2024-01-08 0:33 ` Alistair Francis
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