From: Deepak Gupta <debug@rivosinc.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com,
Kip Walker <kip@rivosinc.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v1 RFC Zisslpcfi 3/9] target/riscv: implements CSRs and new bits in existing CSRs in zisslpcfi
Date: Wed, 15 Feb 2023 17:38:49 -0800 [thread overview]
Message-ID: <CAKC1njR44uKkeqT52mn2wg4PzpF6cvwCEk7cGn=gCVjwjVA-6Q@mail.gmail.com> (raw)
In-Reply-To: <d9f692af-eb86-421d-f0cf-495f2a2e01b4@linaro.org>
On Wed, Feb 15, 2023 at 4:02 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 2/15/23 13:33, Deepak Gupta wrote:
> > On Tue, Feb 14, 2023 at 9:47 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
> >> And MSTATUS_UBCFIEN field change don't need flush tlb.
> >>
> >
> > TCG code-gen would be different depending on whether ubcfi is enabled or not.
> > As an example a TB might have code generated when bcfi was enabled.
> > But if someone disables it,
> > translation needs to happen again and zimops implementation should be
> > generated this time.
>
> tlb_flush does not affect translation. TB are tied to physical addresses and are only
> flushed by writes or tb_flush().
>
> The correct fix is to allocate a bit from FIELD(TB_FLAGS, X, Y, 1), and adjust
> cpu_get_tb_cpu_state to indicate when CFI is active in the current cpu mode.
>
>
Hmm... So this looks like a major oversight on my side.
I had been under the impression that tlb flush does TB flushes too.
I was trying to save on TB_FLAGS.
I saw `tb_jmp_cache` was being cleared, didn't dig deep and assumed
that tlb flush clears up TB as well.
Now that you've pointed it out, it looks like that's a different optimization.
So looks like this definitely needs a fix.
Question:
I'll basically need two bits (one for forward cfi and one for backward cfi).
But I need to throw away the TB if cfi enabling bits mismatch at the
time TB was generated and the current state of enabling bits.
Reason being, this needs to get translated again and zimops need to be
generated.
What's the best way to throw away a single TB?
> r~
next prev parent reply other threads:[~2023-02-16 1:39 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20230209062404.3582018-1-debug@rivosinc.com>
2023-02-09 6:23 ` [PATCH v1 RFC Zisslpcfi 1/9] target/riscv: adding zimops and zisslpcfi extension to RISCV cpu config Deepak Gupta
2023-02-11 3:19 ` weiwei
2023-02-13 3:15 ` Deepak Gupta
2023-02-15 2:52 ` LIU Zhiwei
2023-02-15 20:47 ` Deepak Gupta
2023-02-16 1:46 ` LIU Zhiwei
2023-02-16 4:20 ` Richard Henderson
2023-02-09 6:23 ` [PATCH v1 RFC Zisslpcfi 2/9] target/riscv: zisslpcfi CSR, bit positions and other definitions Deepak Gupta
2023-02-11 3:32 ` weiwei
2023-02-13 3:21 ` Deepak Gupta
2023-02-15 3:31 ` LIU Zhiwei
2023-02-15 20:42 ` Deepak Gupta
2023-02-09 6:23 ` [PATCH v1 RFC Zisslpcfi 3/9] target/riscv: implements CSRs and new bits in existing CSRs in zisslpcfi Deepak Gupta
2023-02-15 5:47 ` LIU Zhiwei
2023-02-15 6:24 ` LIU Zhiwei
2023-02-15 23:42 ` Deepak Gupta
2023-02-15 23:33 ` Deepak Gupta
2023-02-16 0:02 ` Richard Henderson
2023-02-16 1:38 ` Deepak Gupta [this message]
2023-02-16 2:43 ` Richard Henderson
2023-02-16 5:20 ` Deepak Gupta
2023-02-09 6:23 ` [PATCH v1 RFC Zisslpcfi 4/9] target/riscv: helper functions for forward and backward cfi Deepak Gupta
2023-02-15 6:26 ` LIU Zhiwei
2023-02-15 23:35 ` Deepak Gupta
2023-02-09 6:24 ` [PATCH v1 RFC Zisslpcfi 5/9] target/riscv: state save and restore of zisslppcfi state Deepak Gupta
2023-02-15 6:10 ` LIU Zhiwei
2023-02-15 23:13 ` Deepak Gupta
2023-02-09 6:24 ` [PATCH v1 RFC Zisslpcfi 6/9] target/riscv: MMU changes for back cfi's shadow stack Deepak Gupta
2023-02-15 8:43 ` LIU Zhiwei
2023-02-15 23:57 ` Deepak Gupta
2023-02-16 2:36 ` LIU Zhiwei
2023-02-16 5:43 ` Deepak Gupta
2023-02-09 6:24 ` [PATCH v1 RFC Zisslpcfi 7/9] target/riscv: Tracking indirect branches (fcfi) using TCG Deepak Gupta
2023-02-15 8:55 ` LIU Zhiwei
2023-02-16 0:02 ` Deepak Gupta
2023-02-16 2:43 ` LIU Zhiwei
2023-02-16 5:45 ` Deepak Gupta
2023-02-16 6:05 ` Richard Henderson
2023-02-09 6:24 ` [PATCH v1 RFC Zisslpcfi 8/9] target/riscv: Instructions encodings, implementation and handlers Deepak Gupta
2023-02-15 10:43 ` LIU Zhiwei
2023-02-09 6:24 ` [PATCH v1 RFC Zisslpcfi 9/9] target/riscv: diassembly support for zisslpcfi instructions Deepak Gupta
2023-02-09 6:29 [PATCH v1 RFC Zisslpcfi 0/9] zimops and zisslpcfi extension to riscv Deepak Gupta
2023-02-09 6:29 ` [PATCH v1 RFC Zisslpcfi 3/9] target/riscv: implements CSRs and new bits in existing CSRs in zisslpcfi Deepak Gupta
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