From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76348C636D4 for ; Wed, 15 Feb 2023 23:15:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pSQyP-0006Xu-Hu; Wed, 15 Feb 2023 18:14:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pSQyO-0006XP-0U for qemu-devel@nongnu.org; Wed, 15 Feb 2023 18:14:00 -0500 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pSQyL-0006He-DB for qemu-devel@nongnu.org; Wed, 15 Feb 2023 18:13:59 -0500 Received: by mail-ed1-x530.google.com with SMTP id w3so499273edc.2 for ; Wed, 15 Feb 2023 15:13:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=EhztFA5Q+nmazngAoL8vXMR+vDKNbL+tGotZpUc65dc=; b=hyJuBhE5o0zJgrDGM0L680OVzysBChLQOVR7G/UU/eoTuF/QGb9HsnGACwFnNsXtul kn+4R8CGbyXVXnadgL9uWtXP//uViLeRsdpPA9mfdQnh+rwdsSQN6j/rPr8r5S4tlrqh 33iySqevu+lFthX4lobw7t8TXCiG6gByU4OiW5wL7UY89v7Q5cSg4wVtNhpZ6YV0pMJE r+v8ZyMY6w8rYfW0aDtwiPQw3QWZxG2ASCeQ1q6s1rXyEvs93+uDQOKW/opsQjNGqDIX w+GQR2fANJ3xZarr7CvZtQ/TSoairGyPUn3qhpsp0629LPbTzm1WgVP6sVUQqCFIhfq3 mQeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=EhztFA5Q+nmazngAoL8vXMR+vDKNbL+tGotZpUc65dc=; b=Qg2gx1yWHKJBS8MlWWZLbrPvROqQCddriQmbJ4Phvj6FsfLyCl7g7VGjSb53ntYiVI 23mV2j5oZckvEe5yemtcCOu9HcMYhpudwt+svNedA2KkkXovBDzz/yHiMkFvsehQ796i HlGAscQuLabvVrceFl6/xCdsZfzU9dqKVuYh+XDmQ7AZHAfrGPnUiXCBkABMNsmQ9UvP 3Nc3XNUgnjmiadK9BZovD1LQF35BAKZFgouFhRfjCDt6LQ//t6fJjop4G76ihI5JlZKc J5G5GeKrY5+MGo944rKym0SQ+4Fuifjuo3i8SBm+TFjZngp5ozIL7hL6N4EsXRjTzT1/ 1wpQ== X-Gm-Message-State: AO0yUKV2vUZnoGLd2uesQalhZ/6sHPUWKCWPnvzkI+tmdoiINsMknunE FZo+xs0bUgfBMaYo2z97PxpsFkteISVF/L/hki+AlA== X-Google-Smtp-Source: AK7set+rgSg7j+qryPXpFspUMUYYEZSXK6B1DKJpAjFqsG6IJSMDTm7xowdL6gKQPtG7FEesAqqKZ/xdaf0D8p3kZLU= X-Received: by 2002:a05:6402:f21:b0:4ac:e5d4:e13f with SMTP id i33-20020a0564020f2100b004ace5d4e13fmr185797eda.3.1676502834430; Wed, 15 Feb 2023 15:13:54 -0800 (PST) MIME-Version: 1.0 References: <20230209062404.3582018-1-debug@rivosinc.com> <20230209062404.3582018-6-debug@rivosinc.com> In-Reply-To: From: Deepak Gupta Date: Wed, 15 Feb 2023 15:13:34 -0800 Message-ID: Subject: Re: [PATCH v1 RFC Zisslpcfi 5/9] target/riscv: state save and restore of zisslppcfi state To: LIU Zhiwei Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, Kip Walker , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=debug@rivosinc.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Feb 14, 2023 at 10:11 PM LIU Zhiwei wrote: > > > On 2023/2/9 14:24, Deepak Gupta wrote: > > zisslpcfi's forward cfi if enabled on a hart, enables tracking of > > indirect branches. CPU/hart internally keeps a state `elp` short > > for expecting landing pad instruction. This state goes into > > LP_EXPECTED on an indirect branch. But an interrupt/exception can occur > > before target instruction is executed. In such a case this state must be > > preserved so that it can be restored later. zisslpcfi saves elp state in > > `sstatus` CSR. > > And mstatus CSR. Noted. > > Otherwise, > > Reviewed-by: LIU Zhiwei > > > This patch saves elp state in sstatus CSR on trap delivery > > while restores from sstatus CSR on trap return. > > > > Additionally state in sstatus CSR must have save and restore zisslpcfi > > state on exiting from hypervisor and entering into hypervisor. > > > > Signed-off-by: Deepak Gupta > > Signed-off-by: Kip Walker > > --- > > target/riscv/cpu_bits.h | 5 +++++ > > target/riscv/cpu_helper.c | 26 ++++++++++++++++++++++++++ > > target/riscv/op_helper.c | 12 ++++++++++++ > > 3 files changed, 43 insertions(+) > > > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > > index 1663ba5775..37100ec8f6 100644 > > --- a/target/riscv/cpu_bits.h > > +++ b/target/riscv/cpu_bits.h > > @@ -594,6 +594,11 @@ typedef enum { > > > > #define CFISTATUS_S_MASK (SSTATUS_UFCFIEN | SSTATUS_UBCFIEN | \ > > SSTATUS_SPELP) > > +/* enum for branch tracking state in cpu/hart */ > > +typedef enum { > > + NO_LP_EXPECTED = 0, > > + LP_EXPECTED = 1, > > +} cfi_elp; > > > > /* hstatus CSR bits */ > > #define HSTATUS_VSBE 0x00000020 > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > index a397023840..fc188683c9 100644 > > --- a/target/riscv/cpu_helper.c > > +++ b/target/riscv/cpu_helper.c > > @@ -534,6 +534,16 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) > > if (riscv_has_ext(env, RVF)) { > > mstatus_mask |= MSTATUS_FS; > > } > > + > > + /* > > + * If cfi extension available, menvcfg.CFI = 1 and henvcfg.CFI = 1, > > + * then apply CFI mask on mstatus > > + */ > > + if (env_archcpu(env)->cfg.ext_cfi && > > + get_field(env->menvcfg, MENVCFG_CFI) && > > + get_field(env->henvcfg, HENVCFG_CFI)) { > > + mstatus_mask |= CFISTATUS_S_MASK; > > + } > > bool current_virt = riscv_cpu_virt_enabled(env); > > > > g_assert(riscv_has_ext(env, RVH)); > > @@ -1723,6 +1733,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) > > if (env->priv <= PRV_S && > > cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { > > /* handle the trap in S-mode */ > > + /* save elp status */ > > + if (cpu_get_fcfien(env)) { > > + env->mstatus = set_field(env->mstatus, MSTATUS_SPELP, env->elp); > > + } > > if (riscv_has_ext(env, RVH)) { > > uint64_t hdeleg = async ? env->hideleg : env->hedeleg; > > > > @@ -1772,6 +1786,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) > > riscv_cpu_set_mode(env, PRV_S); > > } else { > > /* handle the trap in M-mode */ > > + /* save elp status */ > > + if (cpu_get_fcfien(env)) { > > + env->mstatus = set_field(env->mstatus, MSTATUS_MPELP, env->elp); > > + } > > if (riscv_has_ext(env, RVH)) { > > if (riscv_cpu_virt_enabled(env)) { > > riscv_cpu_swap_hypervisor_regs(env); > > @@ -1803,6 +1821,14 @@ void riscv_cpu_do_interrupt(CPUState *cs) > > riscv_cpu_set_mode(env, PRV_M); > > } > > > > + /* > > + * Interrupt/exception/trap delivery is asynchronous event and as per > > + * Zisslpcfi spec CPU should clear up the ELP state. If cfi extension is > > + * available, clear ELP state. > > + */ > > + if (cpu->cfg.ext_cfi) { > > + env->elp = NO_LP_EXPECTED; > > + } > > /* NOTE: it is not necessary to yield load reservations here. It is only > > * necessary for an SC from "another hart" to cause a load reservation > > * to be yielded. Refer to the memory consistency model section of the > > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > > index 878bcb03b8..d15893aa82 100644 > > --- a/target/riscv/op_helper.c > > +++ b/target/riscv/op_helper.c > > @@ -176,6 +176,12 @@ target_ulong helper_sret(CPURISCVState *env) > > riscv_cpu_set_virt_enabled(env, prev_virt); > > } > > > > + /* If forward cfi enabled for target, restore elp status */ > > + if (cpu_get_fcfien(env)) { > > + env->elp = get_field(env->mstatus, MSTATUS_SPELP); > > + env->mstatus = set_field(env->mstatus, MSTATUS_SPELP, 0); > > + } > > + > > riscv_cpu_set_mode(env, prev_priv); > > > > return retpc; > > @@ -220,6 +226,12 @@ target_ulong helper_mret(CPURISCVState *env) > > riscv_cpu_set_virt_enabled(env, prev_virt); > > } > > > > + /* If forward cfi enabled for target, restore elp status */ > > + if (cpu_get_fcfien(env)) { > > + env->elp = get_field(env->mstatus, MSTATUS_MPELP); > > + env->mstatus = set_field(env->mstatus, MSTATUS_MPELP, 0); > > + } > > + > > return retpc; > > } > >