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X-Received-From: 2607:f8b0:4864:20::243 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , qemu-block@nongnu.org, "Michael S. Tsirkin" , Aleksandar Rikalo , Qemu Developers , Aleksandar Markovic , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Igor Mammedov , =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , John Snow Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000e61350059497e940 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Philippe Mathieu-Daud=C3=A9 =E4=BA=8E2019=E5=B9=B410=E6= =9C=8810=E6=97=A5=E5=91=A8=E5=9B=9B =E4=B8=8B=E5=8D=889:16=E5=86=99=E9=81= =93=EF=BC=9A > The PIIX/IDE is a PCI device within a PIIX chipset, it will be reset > when the PCI bus it stands on is reset. > > Convert its reset handler into a proper Device reset method. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > Reviewed-by: Li Qiang > --- > v3: Also convert PIIX4 (Li Qiang) > --- > hw/ide/piix.c | 9 ++++----- > 1 file changed, 4 insertions(+), 5 deletions(-) > > diff --git a/hw/ide/piix.c b/hw/ide/piix.c > index fba6bc8bff..db313dd3b1 100644 > --- a/hw/ide/piix.c > +++ b/hw/ide/piix.c > @@ -30,7 +30,6 @@ > #include "sysemu/block-backend.h" > #include "sysemu/blockdev.h" > #include "sysemu/dma.h" > -#include "sysemu/reset.h" > > #include "hw/ide/pci.h" > #include "trace.h" > @@ -103,9 +102,9 @@ static void bmdma_setup_bar(PCIIDEState *d) > } > } > > -static void piix3_reset(void *opaque) > +static void piix_ide_reset(DeviceState *dev) > { > - PCIIDEState *d =3D opaque; > + PCIIDEState *d =3D PCI_IDE(dev); > PCIDevice *pd =3D PCI_DEVICE(d); > uint8_t *pci_conf =3D pd->config; > int i; > @@ -154,8 +153,6 @@ static void pci_piix_ide_realize(PCIDevice *dev, Erro= r > **errp) > > pci_conf[PCI_CLASS_PROG] =3D 0x80; // legacy ATA mode > > - qemu_register_reset(piix3_reset, d); > - > bmdma_setup_bar(d); > pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); > > @@ -247,6 +244,7 @@ static void piix3_ide_class_init(ObjectClass *klass, > void *data) > DeviceClass *dc =3D DEVICE_CLASS(klass); > PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); > > + dc->reset =3D piix_ide_reset; > k->realize =3D pci_piix_ide_realize; > k->exit =3D pci_piix_ide_exitfn; > k->vendor_id =3D PCI_VENDOR_ID_INTEL; > @@ -273,6 +271,7 @@ static void piix4_ide_class_init(ObjectClass *klass, > void *data) > DeviceClass *dc =3D DEVICE_CLASS(klass); > PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); > > + dc->reset =3D piix_ide_reset; > k->realize =3D pci_piix_ide_realize; > k->exit =3D pci_piix_ide_exitfn; > k->vendor_id =3D PCI_VENDOR_ID_INTEL; > -- > 2.21.0 > > --000000000000e61350059497e940 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com> =E4=BA=8E2019=E5= =B9=B410=E6=9C=8810=E6=97=A5=E5=91=A8=E5=9B=9B =E4=B8=8B=E5=8D=889:16=E5=86= =99=E9=81=93=EF=BC=9A
The PIIX/IDE is a PCI device within a PIIX chipset, it will be reset<= br> when the PCI bus it stands on is reset.

Convert its reset handler into a proper Device reset method.

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
<= br>

Reviewed-by: Li Qiang <liq3ea@gmail.com>
=C2=A0
---
v3: Also convert PIIX4 (Li Qiang)
---
=C2=A0hw/ide/piix.c | 9 ++++-----
=C2=A01 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index fba6bc8bff..db313dd3b1 100644
--- a/hw/ide/piix.c
+++ b/hw/ide/piix.c
@@ -30,7 +30,6 @@
=C2=A0#include "sysemu/block-backend.h"
=C2=A0#include "sysemu/blockdev.h"
=C2=A0#include "sysemu/dma.h"
-#include "sysemu/reset.h"

=C2=A0#include "hw/ide/pci.h"
=C2=A0#include "trace.h"
@@ -103,9 +102,9 @@ static void bmdma_setup_bar(PCIIDEState *d)
=C2=A0 =C2=A0 =C2=A0}
=C2=A0}

-static void piix3_reset(void *opaque)
+static void piix_ide_reset(DeviceState *dev)
=C2=A0{
-=C2=A0 =C2=A0 PCIIDEState *d =3D opaque;
+=C2=A0 =C2=A0 PCIIDEState *d =3D PCI_IDE(dev);
=C2=A0 =C2=A0 =C2=A0PCIDevice *pd =3D PCI_DEVICE(d);
=C2=A0 =C2=A0 =C2=A0uint8_t *pci_conf =3D pd->config;
=C2=A0 =C2=A0 =C2=A0int i;
@@ -154,8 +153,6 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error = **errp)

=C2=A0 =C2=A0 =C2=A0pci_conf[PCI_CLASS_PROG] =3D 0x80; // legacy ATA mode
-=C2=A0 =C2=A0 qemu_register_reset(piix3_reset, d);
-
=C2=A0 =C2=A0 =C2=A0bmdma_setup_bar(d);
=C2=A0 =C2=A0 =C2=A0pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &am= p;d->bmdma_bar);

@@ -247,6 +244,7 @@ static void piix3_ide_class_init(ObjectClass *klass, vo= id *data)
=C2=A0 =C2=A0 =C2=A0DeviceClass *dc =3D DEVICE_CLASS(klass);
=C2=A0 =C2=A0 =C2=A0PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass);

+=C2=A0 =C2=A0 dc->reset =3D piix_ide_reset;
=C2=A0 =C2=A0 =C2=A0k->realize =3D pci_piix_ide_realize;
=C2=A0 =C2=A0 =C2=A0k->exit =3D pci_piix_ide_exitfn;
=C2=A0 =C2=A0 =C2=A0k->vendor_id =3D PCI_VENDOR_ID_INTEL;
@@ -273,6 +271,7 @@ static void piix4_ide_class_init(ObjectClass *klass, vo= id *data)
=C2=A0 =C2=A0 =C2=A0DeviceClass *dc =3D DEVICE_CLASS(klass);
=C2=A0 =C2=A0 =C2=A0PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass);

+=C2=A0 =C2=A0 dc->reset =3D piix_ide_reset;
=C2=A0 =C2=A0 =C2=A0k->realize =3D pci_piix_ide_realize;
=C2=A0 =C2=A0 =C2=A0k->exit =3D pci_piix_ide_exitfn;
=C2=A0 =C2=A0 =C2=A0k->vendor_id =3D PCI_VENDOR_ID_INTEL;
--
2.21.0

--000000000000e61350059497e940--