From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5DB92C25B75 for ; Thu, 30 May 2024 03:31:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sCWV4-0008S0-PR; Wed, 29 May 2024 23:30:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sCWV3-0008RQ-4G for qemu-devel@nongnu.org; Wed, 29 May 2024 23:30:45 -0400 Received: from mail-ua1-x933.google.com ([2607:f8b0:4864:20::933]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sCWV0-0007u5-0h for qemu-devel@nongnu.org; Wed, 29 May 2024 23:30:43 -0400 Received: by mail-ua1-x933.google.com with SMTP id a1e0cc1a2514c-80ad0bb602eso26144241.1 for ; Wed, 29 May 2024 20:30:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717039840; x=1717644640; darn=nongnu.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=jdo4tjkmUiqNVp7+LlkCxwwqZd0ECj+B8sj+vTLMz58=; b=mT3h1OOWFE7apRS7fn7XzTe9XlVQvHMQW+f7Nk5rtffH+9B+yXpscgYZv4zijTfPC9 h9BJ84+Yv3SYIhXQyeLQpy+H/1Fo5PRn3SQSWNab/jZJAq2GljbGj3saDaxfGv0pN1IZ 96CJil+nDeQrxgNMGG34f4CiO+5PPdvZEpO2aq5Or4eARxtPJtPhKi+ZN7L0y9B8NAuR uUKc/EYD/UJ6UrPmTXNkL5WQK9kGh2CYsuVHjFc7Z+u1DQ63tOcbmi8I7c1EBwOW5/8/ LsQPB8Hdq7+D/is8XGcd8vQ5+JjRrAJiFStBPvxsA0lX3e39MLFKplGNNfZxB4uuf1Rp D19w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717039840; x=1717644640; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=jdo4tjkmUiqNVp7+LlkCxwwqZd0ECj+B8sj+vTLMz58=; b=flNLztJr3so1TFGgNVu+QJ2WNOakyDZ4nu1xbPXAAdxprZCuIE4UKiesZalYX+GkK8 fS6eSGomsdienKQ3fda6X3EOcYhHpU8MvpsR6ExrS2wnYedkmvrQ8kSoMK27YCHvAfkp Y0rui9rEEAh3o9CMAsIOOiEtb0q4j4CihNv964y+mPtzOUxOEpIX9+Qpo8HM8G+Lf7Ym 9jawosGFVRBtF3qSnbKArdD/tfq9H36vNe+7HYrwwXDQESTmHw4tk6Vj/YUhgYgfn/t/ J77rJ21/G4WW6lvib3T9NrlCNtWJmI5fx9f+hKxWVVerbJyQhdUzMk5c9/t9vjrv4gwt 5PVA== X-Gm-Message-State: AOJu0YywSIGaYCyRGSvBRpW41SiMG3VvU9Vsg4yMTPzfCitMEgcMgp0p M+lBRjCrGBusDtV2tnq52gFENiipj55aPirSaMe0ZgRi4bDCpueZY1F3p5eIWKuhBhzmUldAuRI /u7TTqWNgUVMErC6OOxhL5EbriG59wvhQfDr3oQ== X-Google-Smtp-Source: AGHT+IFaxFdcol8HakCO1g3a5UqvW+pmTtEbd/uBxawxKzShkIbDhdrBHwHb+ZDCOOT277C74MB4xriAoHDgsPyTnjs= X-Received: by 2002:a05:6122:181f:b0:4e4:eab4:ba2a with SMTP id 71dfb90a1353d-4eaf2493ca3mr1155609e0c.16.1717039840458; Wed, 29 May 2024 20:30:40 -0700 (PDT) MIME-Version: 1.0 References: <20240515080605.2675399-1-fea.wang@sifive.com> <4d2d56aa-5758-4320-a5ef-53ebb87ab494@ventanamicro.com> In-Reply-To: <4d2d56aa-5758-4320-a5ef-53ebb87ab494@ventanamicro.com> From: Fea Wang Date: Thu, 30 May 2024 11:30:28 +0800 Message-ID: Subject: Re: [RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei Content-Type: multipart/alternative; boundary="000000000000c195900619a37dd2" Received-SPF: pass client-ip=2607:f8b0:4864:20::933; envelope-from=fea.wang@sifive.com; helo=mail-ua1-x933.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --000000000000c195900619a37dd2 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Daniel, thank you for your help. I found that only the cover is without many maintainers. I used to send patches by git send-email --dry-run --to 'qemu-devel@nongnu.org, qemu-riscv@nongnu.org' --cc-cmd=3D'scripts/get_maintainer.pl -i' patches/*. Do you have a better script for me? Thank you. Sincerely, Fea On Mon, May 27, 2024 at 5:21=E2=80=AFPM Daniel Henrique Barboza < dbarboza@ventanamicro.com> wrote: > Fea, > > Please try to also add all RISC-V QEMU maintainers and reviewers when > sending > patches. It will get your patches reviewed and queued faster. Otherwise t= he > maintainers can miss you your series due to high ML traffic. > > You can fetch who you want to CC using the get_maintainer.pl script with > the > patch files or any source file in particular, e.g.: > > $ ./scripts/get_maintainer.pl -f target/riscv/cpu.c > Palmer Dabbelt (supporter:RISC-V TCG CPUs) > Alistair Francis (supporter:RISC-V TCG CPUs) > Bin Meng (supporter:RISC-V TCG CPUs) > Weiwei Li (reviewer:RISC-V TCG CPUs) > Daniel Henrique Barboza (reviewer:RISC-V TCG > CPUs) > Liu Zhiwei (reviewer:RISC-V TCG CPUs) > qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) > qemu-devel@nongnu.org (open list:All patches CC here) > > > I added the extra folk in the CC for this reply so don't worry about it. > > > Alistair, please queue this series. It's already fully acked and I would > like to add > some bits on top of the priv_spec 1.13 support. > > > Thanks, > > > Daniel > > On 5/15/24 05:05, Fea.Wang wrote: > > Based on the change log for the RISC-V privilege 1.13 spec, add the > > support for ss1p13. > > > > Ref: > https://github.com/riscv/riscv-isa-manual/blob/a7d93c9/src/priv-preface.a= doc?plain=3D1#L40-L72 > > > > Lists what to do without clarification or document format. > > * Redefined misa.MXL to be read-only, making MXLEN a constant.(Skip, > implementation ignored) > > * Added the constraint that SXLEN=E2=89=A5UXLEN.(Skip, implementation i= gnored) > > * Defined the misa.V field to reflect that the V extension has been > implemented.(Skip, existed) > > * Defined the RV32-only medelegh and hedelegh CSRs.(Done in these > patches) > > * Defined the misaligned atomicity granule PMA, superseding the propose= d > Zam extension..(Skip, implementation ignored) > > * Allocated interrupt 13 for Sscofpmf LCOFI interrupt.(Skip, existed) > > * Defined hardware error and software check exception codes.(Done in > these patches) > > * Specified synchronization requirements when changing the PBMTE fields > in menvcfg and henvcfg.(Skip, implementation ignored) > > * Incorporated Svade and Svadu extension specifications.(Skip, existed) > > > > > > Fea.Wang (4): > > target/riscv: Support the version for ss1p13 > > target/riscv: Add 'P1P13' bit in SMSTATEEN0 > > target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 > > target/riscv: Reserve exception codes for sw-check and hw-err > > > > Jim Shu (1): > > target/riscv: Reuse the conversion function of priv_spec > > > > target/riscv/cpu.c | 8 ++++++-- > > target/riscv/cpu.h | 5 ++++- > > target/riscv/cpu_bits.h | 5 +++++ > > target/riscv/cpu_cfg.h | 1 + > > target/riscv/csr.c | 39 +++++++++++++++++++++++++++++++++++++= + > > target/riscv/tcg/tcg-cpu.c | 17 ++++++++--------- > > 6 files changed, 63 insertions(+), 12 deletions(-) > > > --000000000000c195900619a37dd2 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi=C2=A0Daniel,
thank you for your help.
I found that only the cover is without many maintainers. I used= to send patches by git s= end-email --dry-run --to 'qemu= -devel@nongnu.org,qemu-riscv@n= ongnu.org' --cc-cmd=3D'scripts/get_maintainer.pl -i' patches/*. Do you have a better s= cript for me?
Thank you.

Sincerely,
Fea

On Mon, May 27, 2024 at 5:21=E2=80=AFPM Daniel Henrique Bar= boza <dbarboza@ventanamicro= .com> wrote:
Fea,

Please try to also add all RISC-V QEMU maintainers and reviewers when sendi= ng
patches. It will get your patches reviewed and queued faster. Otherwise the=
maintainers can miss you your series due to high ML traffic.

You can fetch who you want to CC using the get_maintainer.pl script with= the
patch files or any source file in particular, e.g.:

$ ./scripts/get_maintainer.pl -f target/riscv/cpu.c
Palmer Dabbelt <= palmer@dabbelt.com> (supporter:RISC-V TCG CPUs)
Alistair Francis <alistair.francis@wdc.com> (supporter:RISC-V TCG CPUs)
Bin Meng <bmeng.= cn@gmail.com> (supporter:RISC-V TCG CPUs)
Weiwei Li <liwe= i1518@gmail.com> (reviewer:RISC-V TCG CPUs)
Daniel Henrique Barboza <dbarboza@ventanamicro.com> (reviewer:RISC-V TCG CPUs= )
Liu Zhiwei <zhiwei_liu@linux.alibaba.com> (reviewer:RISC-V TCG CPUs)
qemu-riscv@nongn= u.org (open list:RISC-V TCG CPUs)
qemu-devel@nongn= u.org (open list:All patches CC here)


I added the extra folk in the CC for this reply so don't worry about it= .


Alistair, please queue this series. It's already fully acked and I woul= d like to add
some bits on top of the priv_spec 1.13 support.


Thanks,


Daniel

On 5/15/24 05:05, Fea.Wang wrote:
> Based on the change log for the RISC-V privilege 1.13 spec, add the > support for ss1p13.
>
> Ref:https://github.com/riscv/riscv-isa-manual/blob/a7d93c9/src/priv-preface.= adoc?plain=3D1#L40-L72
>
> Lists what to do without clarification or document format.
> * Redefined misa.MXL to be read-only, making MXLEN a constant.(Skip, i= mplementation ignored)
> * Added the constraint that SXLEN=E2=89=A5UXLEN.(Skip, implementation = ignored)
> * Defined the misa.V field to reflect that the V extension has been im= plemented.(Skip, existed)
> * Defined the RV32-only medelegh and hedelegh CSRs.(Done in these patc= hes)
> * Defined the misaligned atomicity granule PMA, superseding the propos= ed Zam extension..(Skip, implementation ignored)
> * Allocated interrupt 13 for Sscofpmf LCOFI interrupt.(Skip, existed)<= br> > * Defined hardware error and software check exception codes.(Done in t= hese patches)
> * Specified synchronization requirements when changing the PBMTE field= s in menvcfg and henvcfg.(Skip, implementation ignored)
> * Incorporated Svade and Svadu extension specifications.(Skip, existed= )
>
>
> Fea.Wang (4):
>=C2=A0 =C2=A0 target/riscv: Support the version for ss1p13
>=C2=A0 =C2=A0 target/riscv: Add 'P1P13' bit in SMSTATEEN0
>=C2=A0 =C2=A0 target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
>=C2=A0 =C2=A0 target/riscv: Reserve exception codes for sw-check and hw= -err
>
> Jim Shu (1):
>=C2=A0 =C2=A0 target/riscv: Reuse the conversion function of priv_spec<= br> >
>=C2=A0 =C2=A0target/riscv/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2= =A0 8 ++++++--
>=C2=A0 =C2=A0target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2= =A0 5 ++++-
>=C2=A0 =C2=A0target/riscv/cpu_bits.h=C2=A0 =C2=A0 |=C2=A0 5 +++++
>=C2=A0 =C2=A0target/riscv/cpu_cfg.h=C2=A0 =C2=A0 =C2=A0|=C2=A0 1 +
>=C2=A0 =C2=A0target/riscv/csr.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 39 += +++++++++++++++++++++++++++++++++++++
>=C2=A0 =C2=A0target/riscv/tcg/tcg-cpu.c | 17 ++++++++---------
>=C2=A0 =C2=A06 files changed, 63 insertions(+), 12 deletions(-)
>
--000000000000c195900619a37dd2--