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b=BDlMZO0qBiW9Q4DXQW/oIHytJZ7j+VIe0Xy/+TI3/NFjchkitChNmMwNKYJACOG6al /BsPzgeR6cci2vUFzuoA2tvEyo/SqW/SEL21BwYwPzrLS19P5zdrss6XXdOrVceEpgTT D6FDV9DlpM91Zjw3JjesEQVGT6UN+SpHW9QbjCJ7cVGxBnmZJhoO559wZwoMjQry7abO a46XdbjqTPG/HWqJrweri/lnSitBrCd8WtUna8RkjkRyvmiNr+G2GS2fapkFlo2OsE32 7QmsEU4wdwdSN9j4yH5UPlI4TSayCPTuQA7xX8CsPzepN+o6/B520nnHwhp0UzMLxz8P n4uQ== X-Gm-Message-State: AFqh2ko07qadGRbG2QeUrouEipYCGq2+weMhTrOBBcgJkVJh3FfGXqrT npVfQupYMW0ggBesTufR/fwyrXH9qXqtKLpq4nfwgKgOyc+fZg== X-Google-Smtp-Source: AMrXdXv76femOoULSriQFuJWZ6lCW4kKNKGrffAJcqlgJI/N773qR1e6j6ac+mXzbTkWaZTiwdDHKtkbv1y2Q/e/E0U= X-Received: by 2002:a05:6102:f8c:b0:3c9:8cc2:dd04 with SMTP id e12-20020a0561020f8c00b003c98cc2dd04mr3709032vsv.73.1672835479281; Wed, 04 Jan 2023 04:31:19 -0800 (PST) MIME-Version: 1.0 References: <20221221224022.425831-1-alistair.francis@opensource.wdc.com> <20221221224022.425831-4-alistair.francis@opensource.wdc.com> In-Reply-To: <20221221224022.425831-4-alistair.francis@opensource.wdc.com> From: Alistair Francis Date: Wed, 4 Jan 2023 22:30:52 +1000 Message-ID: Subject: Re: [PULL v2 03/45] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro To: Alistair Francis Cc: qemu-devel@nongnu.org, Wilfred Mallawa , Alistair Francis Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e32; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe32.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Dec 22, 2022 at 8:40 AM Alistair Francis wrote: > > From: Wilfred Mallawa > > use the `FIELD32_1CLEAR` macro to implement register > `rw1c` functionality to `ibex_spi`. > > This change was tested by running the `SPI_HOST` from TockOS. > > Signed-off-by: Wilfred Mallawa > Reviewed-by: Alistair Francis > Message-Id: <20221017054950.317584-3-wilfred.mallawa@opensource.wdc.com> > Signed-off-by: Alistair Francis > --- > hw/ssi/ibex_spi_host.c | 21 +++++++++------------ > 1 file changed, 9 insertions(+), 12 deletions(-) > > diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c > index 57df462e3c..0a456cd1ed 100644 > --- a/hw/ssi/ibex_spi_host.c > +++ b/hw/ssi/ibex_spi_host.c > @@ -342,7 +342,7 @@ static void ibex_spi_host_write(void *opaque, hwaddr addr, > { > IbexSPIHostState *s = opaque; > uint32_t val32 = val64; > - uint32_t shift_mask = 0xff, status = 0, data = 0; > + uint32_t shift_mask = 0xff, status = 0; > uint8_t txqd_len; > > trace_ibex_spi_host_write(addr, size, val64); > @@ -355,12 +355,11 @@ static void ibex_spi_host_write(void *opaque, hwaddr addr, > case IBEX_SPI_HOST_INTR_STATE: > /* rw1c status register */ > if (FIELD_EX32(val32, INTR_STATE, ERROR)) { > - data = FIELD_DP32(data, INTR_STATE, ERROR, 0); > + s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], INTR_STATE, ERROR); It seems that this change doesn't build on Windows (https://cirrus-ci.com/task/6444497832247296?logs=main#L2163) Maybe ERROR is reserved? Either way I'll have to drop this commit. Maybe just drop this change and keep the rest? Alistair > } > if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) { > - data = FIELD_DP32(data, INTR_STATE, SPI_EVENT, 0); > + s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], INTR_STATE, SPI_EVENT); > } > - s->regs[addr] = data; > break; > case IBEX_SPI_HOST_INTR_ENABLE: > s->regs[addr] = val32; > @@ -505,27 +504,25 @@ static void ibex_spi_host_write(void *opaque, hwaddr addr, > * When an error occurs, the corresponding bit must be cleared > * here before issuing any further commands > */ > - status = s->regs[addr]; > /* rw1c status register */ > if (FIELD_EX32(val32, ERROR_STATUS, CMDBUSY)) { > - status = FIELD_DP32(status, ERROR_STATUS, CMDBUSY, 0); > + s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, CMDBUSY); > } > if (FIELD_EX32(val32, ERROR_STATUS, OVERFLOW)) { > - status = FIELD_DP32(status, ERROR_STATUS, OVERFLOW, 0); > + s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, OVERFLOW); > } > if (FIELD_EX32(val32, ERROR_STATUS, UNDERFLOW)) { > - status = FIELD_DP32(status, ERROR_STATUS, UNDERFLOW, 0); > + s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, UNDERFLOW); > } > if (FIELD_EX32(val32, ERROR_STATUS, CMDINVAL)) { > - status = FIELD_DP32(status, ERROR_STATUS, CMDINVAL, 0); > + s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, CMDINVAL); > } > if (FIELD_EX32(val32, ERROR_STATUS, CSIDINVAL)) { > - status = FIELD_DP32(status, ERROR_STATUS, CSIDINVAL, 0); > + s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, CSIDINVAL); > } > if (FIELD_EX32(val32, ERROR_STATUS, ACCESSINVAL)) { > - status = FIELD_DP32(status, ERROR_STATUS, ACCESSINVAL, 0); > + s->regs[addr] = FIELD32_1CLEAR(s->regs[addr], ERROR_STATUS, ACCESSINVAL); > } > - s->regs[addr] = status; > break; > case IBEX_SPI_HOST_EVENT_ENABLE: > /* Controls which classes of SPI events raise an interrupt. */ > -- > 2.38.1 >