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Sun, 08 Mar 2026 22:01:52 -0700 (PDT) MIME-Version: 1.0 References: <20260306071105.3328365-1-max.chou@sifive.com> <20260306071105.3328365-6-max.chou@sifive.com> In-Reply-To: <20260306071105.3328365-6-max.chou@sifive.com> From: Alistair Francis Date: Mon, 9 Mar 2026 15:01:26 +1000 X-Gm-Features: AaiRm52bxTnL5rkgzYwVOprXYhbqFNz9T96_6WmkkCAb8-y-etHfwx8vzBoTcuM Message-ID: Subject: Re: [PATCH v5 5/9] target/riscv: Use the tb->cs_base as the extend tb flags To: Max Chou Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=alistair23@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Mar 6, 2026 at 5:13=E2=80=AFPM Max Chou wrote= : > > We have more than 32-bits worth of state per TB, so use the > tb->cs_base, which is otherwise unused for RISC-V, as the extend flag. > > Reviewed-by: Daniel Henrique Barboza > Reviewed-by: Chao Liu > Signed-off-by: Max Chou > --- > include/exec/translation-block.h | 1 + > target/riscv/cpu.h | 3 +++ > target/riscv/tcg/tcg-cpu.c | 7 ++++++- > 3 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/include/exec/translation-block.h b/include/exec/translation-= block.h > index 4f83d5bec9..40cc699031 100644 > --- a/include/exec/translation-block.h > +++ b/include/exec/translation-block.h > @@ -65,6 +65,7 @@ struct TranslationBlock { > * arm: an extension of tb->flags, > * s390x: instruction data for EXECUTE, > * sparc: the next pc of the instruction queue (for delay slots). > + * riscv: an extension of tb->flags, > */ > uint64_t cs_base; > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 962cc45073..4c0676ed53 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -703,6 +703,9 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) > FIELD(TB_FLAGS, PM_PMM, 29, 2) > FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) > > +FIELD(EXT_TB_FLAGS, MISA_EXT, 0, 32) > +FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1) > + > #ifdef TARGET_RISCV32 > #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) > #else > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 720ff0c2a3..378b298886 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -104,6 +104,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState = *cs) > RISCVCPU *cpu =3D env_archcpu(env); > RISCVExtStatus fs, vs; > uint32_t flags =3D 0; > + uint64_t ext_flags =3D 0; > bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); > > if (cpu->cfg.ext_zve32x) { > @@ -118,6 +119,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState = *cs) > > /* lmul encoded as in DisasContext::lmul */ > int8_t lmul =3D sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL),= 0, 3); > + uint8_t altfmt =3D FIELD_EX64(env->vtype, VTYPE, ALTFMT); > uint32_t vsew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); > uint32_t vlmax =3D vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); > uint32_t maxsz =3D vlmax << vsew; > @@ -133,6 +135,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState = *cs) > flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, > FIELD_EX64(env->vtype, VTYPE, VMA)); > flags =3D FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstar= t =3D=3D 0); > + ext_flags =3D FIELD_DP64(ext_flags, EXT_TB_FLAGS, ALTFMT, altfmt= ); > } else { > flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); > } > @@ -189,10 +192,12 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUStat= e *cs) > flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env))= ; > flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); > > + ext_flags =3D FIELD_DP64(ext_flags, EXT_TB_FLAGS, MISA_EXT, env->mis= a_ext); > + > return (TCGTBCPUState){ > .pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc= , > .flags =3D flags, > - .cs_base =3D env->misa_ext, > + .cs_base =3D ext_flags, We need to update the comment in `struct TranslationBlock` for `target_ulong cs_base` Alistair > }; > } > > -- > 2.52.0 > >