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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a2a; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Jan 9, 2024 at 12:05=E2=80=AFPM Atish Patra w= rote: > > From: Kaiwen Xue > > This adds the definitions for ISA extension smcntrpmf. > > Signed-off-by: Kaiwen Xue > Reviewed-by: Daniel Henrique Barboza > Signed-off-by: Atish Patra Acked-by: Alistair Francis Alistair > --- > target/riscv/cpu.h | 6 ++++++ > target/riscv/cpu_bits.h | 29 +++++++++++++++++++++++++++++ > 2 files changed, 35 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index d74b361be641..34617c4c4bab 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -319,6 +319,12 @@ struct CPUArchState { > > target_ulong mcountinhibit; > > + /* PMU cycle & instret privilege mode filtering */ > + target_ulong mcyclecfg; > + target_ulong mcyclecfgh; > + target_ulong minstretcfg; > + target_ulong minstretcfgh; > + > /* PMU counter state */ > PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index ebd7917d490a..0ee91e502e8f 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -401,6 +401,10 @@ > /* Machine counter-inhibit register */ > #define CSR_MCOUNTINHIBIT 0x320 > > +/* Machine counter configuration registers */ > +#define CSR_MCYCLECFG 0x321 > +#define CSR_MINSTRETCFG 0x322 > + > #define CSR_MHPMEVENT3 0x323 > #define CSR_MHPMEVENT4 0x324 > #define CSR_MHPMEVENT5 0x325 > @@ -431,6 +435,9 @@ > #define CSR_MHPMEVENT30 0x33e > #define CSR_MHPMEVENT31 0x33f > > +#define CSR_MCYCLECFGH 0x721 > +#define CSR_MINSTRETCFGH 0x722 > + > #define CSR_MHPMEVENT3H 0x723 > #define CSR_MHPMEVENT4H 0x724 > #define CSR_MHPMEVENT5H 0x725 > @@ -885,6 +892,28 @@ typedef enum RISCVException { > /* PMU related bits */ > #define MIE_LCOFIE (1 << IRQ_PMU_OVF) > > +#define MCYCLECFG_BIT_MINH BIT_ULL(62) > +#define MCYCLECFGH_BIT_MINH BIT(30) > +#define MCYCLECFG_BIT_SINH BIT_ULL(61) > +#define MCYCLECFGH_BIT_SINH BIT(29) > +#define MCYCLECFG_BIT_UINH BIT_ULL(60) > +#define MCYCLECFGH_BIT_UINH BIT(28) > +#define MCYCLECFG_BIT_VSINH BIT_ULL(59) > +#define MCYCLECFGH_BIT_VSINH BIT(27) > +#define MCYCLECFG_BIT_VUINH BIT_ULL(58) > +#define MCYCLECFGH_BIT_VUINH BIT(26) > + > +#define MINSTRETCFG_BIT_MINH BIT_ULL(62) > +#define MINSTRETCFGH_BIT_MINH BIT(30) > +#define MINSTRETCFG_BIT_SINH BIT_ULL(61) > +#define MINSTRETCFGH_BIT_SINH BIT(29) > +#define MINSTRETCFG_BIT_UINH BIT_ULL(60) > +#define MINSTRETCFGH_BIT_UINH BIT(28) > +#define MINSTRETCFG_BIT_VSINH BIT_ULL(59) > +#define MINSTRETCFGH_BIT_VSINH BIT(27) > +#define MINSTRETCFG_BIT_VUINH BIT_ULL(58) > +#define MINSTRETCFGH_BIT_VUINH BIT(26) > + > #define MHPMEVENT_BIT_OF BIT_ULL(63) > #define MHPMEVENTH_BIT_OF BIT(31) > #define MHPMEVENT_BIT_MINH BIT_ULL(62) > -- > 2.34.1 > >