* Re: [PATCH v2 1/1] target/riscv: Add Zihintpause support
[not found] ` <20220524203647.31435-2-daolu@rivosinc.com>
@ 2022-06-07 21:17 ` Dao Lu
2022-06-07 23:03 ` Alistair Francis
0 siblings, 1 reply; 4+ messages in thread
From: Dao Lu @ 2022-06-07 21:17 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V TCG CPUs, Heiko Stuebner
Ping
On Tue, May 24, 2022 at 1:36 PM Dao Lu <daolu@rivosinc.com> wrote:
>
> Tested-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Dao Lu <daolu@rivosinc.com>
> ---
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu.h | 1 +
> target/riscv/insn32.decode | 7 ++++++-
> target/riscv/insn_trans/trans_rvi.c.inc | 18 ++++++++++++++++++
> 4 files changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ccacdee215..183fb37fdf 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -825,6 +825,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> + DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
> DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
> DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
> @@ -996,6 +997,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
> * extensions by an underscore.
> */
> struct isa_ext_data isa_edata_arr[] = {
> + ISA_EDATA_ENTRY(zihintpause, ext_zihintpause),
> ISA_EDATA_ENTRY(zfh, ext_zfh),
> ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
> ISA_EDATA_ENTRY(zfinx, ext_zfinx),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index fe6c9a2c92..e466a04a59 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -394,6 +394,7 @@ struct RISCVCPUConfig {
> bool ext_counters;
> bool ext_ifencei;
> bool ext_icsr;
> + bool ext_zihintpause;
> bool ext_svinval;
> bool ext_svnapot;
> bool ext_svpbmt;
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 4033565393..595fdcdad8 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -149,7 +149,12 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r
> sra 0100000 ..... ..... 101 ..... 0110011 @r
> or 0000000 ..... ..... 110 ..... 0110011 @r
> and 0000000 ..... ..... 111 ..... 0110011 @r
> -fence ---- pred:4 succ:4 ----- 000 ----- 0001111
> +
> +{
> + pause 0000 0001 0000 00000 000 00000 0001111
> + fence ---- pred:4 succ:4 ----- 000 ----- 0001111
> +}
> +
> fence_i ---- ---- ---- ----- 001 ----- 0001111
> csrrw ............ ..... 001 ..... 1110011 @csr
> csrrs ............ ..... 010 ..... 1110011 @csr
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index f1342f30f8..ca75e05f4b 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -796,6 +796,24 @@ static bool trans_srad(DisasContext *ctx, arg_srad *a)
> return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
> }
>
> +static bool trans_pause(DisasContext *ctx, arg_pause *a)
> +{
> + if (!ctx->cfg_ptr->ext_zihintpause) {
> + return false;
> + }
> +
> + /*
> + * PAUSE is a no-op in QEMU,
> + * however we need to clear the reservation,
> + * end the TB and return to main loop
> + */
> + tcg_gen_movi_tl(load_res, -1);
> + gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> + tcg_gen_exit_tb(NULL, 0);
> + ctx->base.is_jmp = DISAS_NORETURN;
> +
> + return true;
> +}
>
> static bool trans_fence(DisasContext *ctx, arg_fence *a)
> {
> --
> 2.30.1 (Apple Git-130)
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 1/1] target/riscv: Add Zihintpause support
2022-06-07 21:17 ` [PATCH v2 1/1] target/riscv: Add Zihintpause support Dao Lu
@ 2022-06-07 23:03 ` Alistair Francis
2022-06-07 23:20 ` Dao Lu
0 siblings, 1 reply; 4+ messages in thread
From: Alistair Francis @ 2022-06-07 23:03 UTC (permalink / raw)
To: Dao Lu
Cc: qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, Bin Meng, open list:RISC-V TCG CPUs,
Heiko Stuebner
On Wed, Jun 8, 2022 at 8:59 AM Dao Lu <daolu@rivosinc.com> wrote:
>
> Ping
The latest version of this patch on the mailing list has comments that
need to be addressed
Alistair
>
> On Tue, May 24, 2022 at 1:36 PM Dao Lu <daolu@rivosinc.com> wrote:
> >
> > Tested-by: Heiko Stuebner <heiko@sntech.de>
> > Signed-off-by: Dao Lu <daolu@rivosinc.com>
> > ---
> > target/riscv/cpu.c | 2 ++
> > target/riscv/cpu.h | 1 +
> > target/riscv/insn32.decode | 7 ++++++-
> > target/riscv/insn_trans/trans_rvi.c.inc | 18 ++++++++++++++++++
> > 4 files changed, 27 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index ccacdee215..183fb37fdf 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -825,6 +825,7 @@ static Property riscv_cpu_properties[] = {
> > DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> > + DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
> > DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
> > DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> > DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
> > @@ -996,6 +997,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
> > * extensions by an underscore.
> > */
> > struct isa_ext_data isa_edata_arr[] = {
> > + ISA_EDATA_ENTRY(zihintpause, ext_zihintpause),
> > ISA_EDATA_ENTRY(zfh, ext_zfh),
> > ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
> > ISA_EDATA_ENTRY(zfinx, ext_zfinx),
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index fe6c9a2c92..e466a04a59 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -394,6 +394,7 @@ struct RISCVCPUConfig {
> > bool ext_counters;
> > bool ext_ifencei;
> > bool ext_icsr;
> > + bool ext_zihintpause;
> > bool ext_svinval;
> > bool ext_svnapot;
> > bool ext_svpbmt;
> > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> > index 4033565393..595fdcdad8 100644
> > --- a/target/riscv/insn32.decode
> > +++ b/target/riscv/insn32.decode
> > @@ -149,7 +149,12 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r
> > sra 0100000 ..... ..... 101 ..... 0110011 @r
> > or 0000000 ..... ..... 110 ..... 0110011 @r
> > and 0000000 ..... ..... 111 ..... 0110011 @r
> > -fence ---- pred:4 succ:4 ----- 000 ----- 0001111
> > +
> > +{
> > + pause 0000 0001 0000 00000 000 00000 0001111
> > + fence ---- pred:4 succ:4 ----- 000 ----- 0001111
> > +}
> > +
> > fence_i ---- ---- ---- ----- 001 ----- 0001111
> > csrrw ............ ..... 001 ..... 1110011 @csr
> > csrrs ............ ..... 010 ..... 1110011 @csr
> > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> > index f1342f30f8..ca75e05f4b 100644
> > --- a/target/riscv/insn_trans/trans_rvi.c.inc
> > +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> > @@ -796,6 +796,24 @@ static bool trans_srad(DisasContext *ctx, arg_srad *a)
> > return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
> > }
> >
> > +static bool trans_pause(DisasContext *ctx, arg_pause *a)
> > +{
> > + if (!ctx->cfg_ptr->ext_zihintpause) {
> > + return false;
> > + }
> > +
> > + /*
> > + * PAUSE is a no-op in QEMU,
> > + * however we need to clear the reservation,
> > + * end the TB and return to main loop
> > + */
> > + tcg_gen_movi_tl(load_res, -1);
> > + gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> > + tcg_gen_exit_tb(NULL, 0);
> > + ctx->base.is_jmp = DISAS_NORETURN;
> > +
> > + return true;
> > +}
> >
> > static bool trans_fence(DisasContext *ctx, arg_fence *a)
> > {
> > --
> > 2.30.1 (Apple Git-130)
> >
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 1/1] target/riscv: Add Zihintpause support
2022-06-07 23:03 ` Alistair Francis
@ 2022-06-07 23:20 ` Dao Lu
2022-06-08 0:03 ` Alistair Francis
0 siblings, 1 reply; 4+ messages in thread
From: Dao Lu @ 2022-06-07 23:20 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, Bin Meng, open list:RISC-V TCG CPUs,
Heiko Stuebner
Hi Alistair,
Thanks for the response. I don't think I can find any comments
on this patch though, could you help point me to them?
Thanks,
Dao
On Tue, Jun 7, 2022 at 4:04 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, Jun 8, 2022 at 8:59 AM Dao Lu <daolu@rivosinc.com> wrote:
> >
> > Ping
>
> The latest version of this patch on the mailing list has comments that
> need to be addressed
>
> Alistair
>
> >
> > On Tue, May 24, 2022 at 1:36 PM Dao Lu <daolu@rivosinc.com> wrote:
> > >
> > > Tested-by: Heiko Stuebner <heiko@sntech.de>
> > > Signed-off-by: Dao Lu <daolu@rivosinc.com>
> > > ---
> > > target/riscv/cpu.c | 2 ++
> > > target/riscv/cpu.h | 1 +
> > > target/riscv/insn32.decode | 7 ++++++-
> > > target/riscv/insn_trans/trans_rvi.c.inc | 18 ++++++++++++++++++
> > > 4 files changed, 27 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > index ccacdee215..183fb37fdf 100644
> > > --- a/target/riscv/cpu.c
> > > +++ b/target/riscv/cpu.c
> > > @@ -825,6 +825,7 @@ static Property riscv_cpu_properties[] = {
> > > DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> > > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> > > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> > > + DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
> > > DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
> > > DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> > > DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
> > > @@ -996,6 +997,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
> > > * extensions by an underscore.
> > > */
> > > struct isa_ext_data isa_edata_arr[] = {
> > > + ISA_EDATA_ENTRY(zihintpause, ext_zihintpause),
> > > ISA_EDATA_ENTRY(zfh, ext_zfh),
> > > ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
> > > ISA_EDATA_ENTRY(zfinx, ext_zfinx),
> > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > > index fe6c9a2c92..e466a04a59 100644
> > > --- a/target/riscv/cpu.h
> > > +++ b/target/riscv/cpu.h
> > > @@ -394,6 +394,7 @@ struct RISCVCPUConfig {
> > > bool ext_counters;
> > > bool ext_ifencei;
> > > bool ext_icsr;
> > > + bool ext_zihintpause;
> > > bool ext_svinval;
> > > bool ext_svnapot;
> > > bool ext_svpbmt;
> > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> > > index 4033565393..595fdcdad8 100644
> > > --- a/target/riscv/insn32.decode
> > > +++ b/target/riscv/insn32.decode
> > > @@ -149,7 +149,12 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r
> > > sra 0100000 ..... ..... 101 ..... 0110011 @r
> > > or 0000000 ..... ..... 110 ..... 0110011 @r
> > > and 0000000 ..... ..... 111 ..... 0110011 @r
> > > -fence ---- pred:4 succ:4 ----- 000 ----- 0001111
> > > +
> > > +{
> > > + pause 0000 0001 0000 00000 000 00000 0001111
> > > + fence ---- pred:4 succ:4 ----- 000 ----- 0001111
> > > +}
> > > +
> > > fence_i ---- ---- ---- ----- 001 ----- 0001111
> > > csrrw ............ ..... 001 ..... 1110011 @csr
> > > csrrs ............ ..... 010 ..... 1110011 @csr
> > > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> > > index f1342f30f8..ca75e05f4b 100644
> > > --- a/target/riscv/insn_trans/trans_rvi.c.inc
> > > +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> > > @@ -796,6 +796,24 @@ static bool trans_srad(DisasContext *ctx, arg_srad *a)
> > > return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
> > > }
> > >
> > > +static bool trans_pause(DisasContext *ctx, arg_pause *a)
> > > +{
> > > + if (!ctx->cfg_ptr->ext_zihintpause) {
> > > + return false;
> > > + }
> > > +
> > > + /*
> > > + * PAUSE is a no-op in QEMU,
> > > + * however we need to clear the reservation,
> > > + * end the TB and return to main loop
> > > + */
> > > + tcg_gen_movi_tl(load_res, -1);
> > > + gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> > > + tcg_gen_exit_tb(NULL, 0);
> > > + ctx->base.is_jmp = DISAS_NORETURN;
> > > +
> > > + return true;
> > > +}
> > >
> > > static bool trans_fence(DisasContext *ctx, arg_fence *a)
> > > {
> > > --
> > > 2.30.1 (Apple Git-130)
> > >
> >
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 1/1] target/riscv: Add Zihintpause support
2022-06-07 23:20 ` Dao Lu
@ 2022-06-08 0:03 ` Alistair Francis
0 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2022-06-08 0:03 UTC (permalink / raw)
To: Dao Lu
Cc: qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, Bin Meng, open list:RISC-V TCG CPUs,
Heiko Stuebner
On Wed, Jun 8, 2022 at 9:20 AM Dao Lu <daolu@rivosinc.com> wrote:
>
> Hi Alistair,
>
> Thanks for the response. I don't think I can find any comments
> on this patch though, could you help point me to them?
I see a PATCH v1 with comments and then your ping to PATCH v2, but I
don't see the original PATCH v2. It might not have made it to the
list, or maybe I just can't find it. Maybe send a v3 and we can go
from there
Alistair
>
> Thanks,
> Dao
>
> On Tue, Jun 7, 2022 at 4:04 PM Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Wed, Jun 8, 2022 at 8:59 AM Dao Lu <daolu@rivosinc.com> wrote:
> > >
> > > Ping
> >
> > The latest version of this patch on the mailing list has comments that
> > need to be addressed
> >
> > Alistair
> >
> > >
> > > On Tue, May 24, 2022 at 1:36 PM Dao Lu <daolu@rivosinc.com> wrote:
> > > >
> > > > Tested-by: Heiko Stuebner <heiko@sntech.de>
> > > > Signed-off-by: Dao Lu <daolu@rivosinc.com>
> > > > ---
> > > > target/riscv/cpu.c | 2 ++
> > > > target/riscv/cpu.h | 1 +
> > > > target/riscv/insn32.decode | 7 ++++++-
> > > > target/riscv/insn_trans/trans_rvi.c.inc | 18 ++++++++++++++++++
> > > > 4 files changed, 27 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > > index ccacdee215..183fb37fdf 100644
> > > > --- a/target/riscv/cpu.c
> > > > +++ b/target/riscv/cpu.c
> > > > @@ -825,6 +825,7 @@ static Property riscv_cpu_properties[] = {
> > > > DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> > > > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> > > > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> > > > + DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
> > > > DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
> > > > DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> > > > DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
> > > > @@ -996,6 +997,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
> > > > * extensions by an underscore.
> > > > */
> > > > struct isa_ext_data isa_edata_arr[] = {
> > > > + ISA_EDATA_ENTRY(zihintpause, ext_zihintpause),
> > > > ISA_EDATA_ENTRY(zfh, ext_zfh),
> > > > ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
> > > > ISA_EDATA_ENTRY(zfinx, ext_zfinx),
> > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > > > index fe6c9a2c92..e466a04a59 100644
> > > > --- a/target/riscv/cpu.h
> > > > +++ b/target/riscv/cpu.h
> > > > @@ -394,6 +394,7 @@ struct RISCVCPUConfig {
> > > > bool ext_counters;
> > > > bool ext_ifencei;
> > > > bool ext_icsr;
> > > > + bool ext_zihintpause;
> > > > bool ext_svinval;
> > > > bool ext_svnapot;
> > > > bool ext_svpbmt;
> > > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> > > > index 4033565393..595fdcdad8 100644
> > > > --- a/target/riscv/insn32.decode
> > > > +++ b/target/riscv/insn32.decode
> > > > @@ -149,7 +149,12 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r
> > > > sra 0100000 ..... ..... 101 ..... 0110011 @r
> > > > or 0000000 ..... ..... 110 ..... 0110011 @r
> > > > and 0000000 ..... ..... 111 ..... 0110011 @r
> > > > -fence ---- pred:4 succ:4 ----- 000 ----- 0001111
> > > > +
> > > > +{
> > > > + pause 0000 0001 0000 00000 000 00000 0001111
> > > > + fence ---- pred:4 succ:4 ----- 000 ----- 0001111
> > > > +}
> > > > +
> > > > fence_i ---- ---- ---- ----- 001 ----- 0001111
> > > > csrrw ............ ..... 001 ..... 1110011 @csr
> > > > csrrs ............ ..... 010 ..... 1110011 @csr
> > > > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> > > > index f1342f30f8..ca75e05f4b 100644
> > > > --- a/target/riscv/insn_trans/trans_rvi.c.inc
> > > > +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> > > > @@ -796,6 +796,24 @@ static bool trans_srad(DisasContext *ctx, arg_srad *a)
> > > > return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
> > > > }
> > > >
> > > > +static bool trans_pause(DisasContext *ctx, arg_pause *a)
> > > > +{
> > > > + if (!ctx->cfg_ptr->ext_zihintpause) {
> > > > + return false;
> > > > + }
> > > > +
> > > > + /*
> > > > + * PAUSE is a no-op in QEMU,
> > > > + * however we need to clear the reservation,
> > > > + * end the TB and return to main loop
> > > > + */
> > > > + tcg_gen_movi_tl(load_res, -1);
> > > > + gen_set_pc_imm(ctx, ctx->pc_succ_insn);
> > > > + tcg_gen_exit_tb(NULL, 0);
> > > > + ctx->base.is_jmp = DISAS_NORETURN;
> > > > +
> > > > + return true;
> > > > +}
> > > >
> > > > static bool trans_fence(DisasContext *ctx, arg_fence *a)
> > > > {
> > > > --
> > > > 2.30.1 (Apple Git-130)
> > > >
> > >
^ permalink raw reply [flat|nested] 4+ messages in thread
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[not found] <20220524203647.31435-1-daolu@rivosinc.com>
[not found] ` <20220524203647.31435-2-daolu@rivosinc.com>
2022-06-07 21:17 ` [PATCH v2 1/1] target/riscv: Add Zihintpause support Dao Lu
2022-06-07 23:03 ` Alistair Francis
2022-06-07 23:20 ` Dao Lu
2022-06-08 0:03 ` Alistair Francis
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