* [PATCH 0/6] Improve the U/S/H extension related check
@ 2022-07-10 8:23 Weiwei Li
2022-07-10 8:23 ` [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations Weiwei Li
` (5 more replies)
0 siblings, 6 replies; 15+ messages in thread
From: Weiwei Li @ 2022-07-10 8:23 UTC (permalink / raw)
To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, Weiwei Li
This patchset tries to improve the U/S/H related check:
* add check for the supported privilege modes conbinations: only supporting M,
S mode is not a suggested combination
* add check for "H extension depends on I extension"
* add check for csrs only existed when U mode is supported
* fix and simplify the checks in hmode/hmode32
Any suggestions are welcome.
Weiwei Li (6):
target/riscv: add check for supported privilege modes conbinations
target/riscv: H extension depends on I extension
target/riscv: fix checkpatch warning may triggered in csr_ops table
target/riscv: add check for csrs existed with U extension
target/riscv: fix checks in hmode/hmode32
target/riscv: simplify the check in hmode to resue the check in
riscv_csrrw_check
target/riscv/cpu.c | 12 ++
target/riscv/csr.c | 412 ++++++++++++++++++++++++---------------------
2 files changed, 236 insertions(+), 188 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations 2022-07-10 8:23 [PATCH 0/6] Improve the U/S/H extension related check Weiwei Li @ 2022-07-10 8:23 ` Weiwei Li 2022-07-11 5:29 ` Alistair Francis 2022-07-10 8:23 ` [PATCH 2/6] target/riscv: H extension depends on I extension Weiwei Li ` (4 subsequent siblings) 5 siblings, 1 reply; 15+ messages in thread From: Weiwei Li @ 2022-07-10 8:23 UTC (permalink / raw) To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel Cc: wangjunqiang, lazyparser, Weiwei Li - There are 3 suggested privilege modes conbinations listed in the spec: 1) M, 2) M, U 3) M, S, U Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> --- target/riscv/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1bb3973806..0dad6906bc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -636,6 +636,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } + if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { + error_setg(errp, + "Setting S extension without U extension is illegal"); + return; + } + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return; -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations 2022-07-10 8:23 ` [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations Weiwei Li @ 2022-07-11 5:29 ` Alistair Francis 0 siblings, 0 replies; 15+ messages in thread From: Alistair Francis @ 2022-07-11 5:29 UTC (permalink / raw) To: Weiwei Li Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang, Wei Wu (吴伟) On Sun, Jul 10, 2022 at 6:25 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > - There are 3 suggested privilege modes conbinations listed in the spec: > 1) M, 2) M, U 3) M, S, U > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 1bb3973806..0dad6906bc 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -636,6 +636,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > return; > } > > + if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { > + error_setg(errp, > + "Setting S extension without U extension is illegal"); > + return; > + } > + > if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { > error_setg(errp, "F extension requires Zicsr"); > return; > -- > 2.17.1 > > ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/6] target/riscv: H extension depends on I extension 2022-07-10 8:23 [PATCH 0/6] Improve the U/S/H extension related check Weiwei Li 2022-07-10 8:23 ` [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations Weiwei Li @ 2022-07-10 8:23 ` Weiwei Li 2022-07-11 5:29 ` Alistair Francis 2022-07-10 8:23 ` [PATCH 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table Weiwei Li ` (3 subsequent siblings) 5 siblings, 1 reply; 15+ messages in thread From: Weiwei Li @ 2022-07-10 8:23 UTC (permalink / raw) To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel Cc: wangjunqiang, lazyparser, Weiwei Li - add check for "H depends on an I base integer ISA with 32 x registers" Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> --- target/riscv/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0dad6906bc..4e40f26e13 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -642,6 +642,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } + if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { + error_setg(errp, + "H depends on an I base integer ISA with 32 x registers"); + return; + } + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return; -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 2/6] target/riscv: H extension depends on I extension 2022-07-10 8:23 ` [PATCH 2/6] target/riscv: H extension depends on I extension Weiwei Li @ 2022-07-11 5:29 ` Alistair Francis 0 siblings, 0 replies; 15+ messages in thread From: Alistair Francis @ 2022-07-11 5:29 UTC (permalink / raw) To: Weiwei Li Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang, Wei Wu (吴伟) On Sun, Jul 10, 2022 at 6:24 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > - add check for "H depends on an I base integer ISA with 32 x registers" > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 0dad6906bc..4e40f26e13 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -642,6 +642,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > return; > } > > + if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { > + error_setg(errp, > + "H depends on an I base integer ISA with 32 x registers"); > + return; > + } > + > if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { > error_setg(errp, "F extension requires Zicsr"); > return; > -- > 2.17.1 > > ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table 2022-07-10 8:23 [PATCH 0/6] Improve the U/S/H extension related check Weiwei Li 2022-07-10 8:23 ` [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations Weiwei Li 2022-07-10 8:23 ` [PATCH 2/6] target/riscv: H extension depends on I extension Weiwei Li @ 2022-07-10 8:23 ` Weiwei Li 2022-07-11 6:41 ` Alistair Francis 2022-07-10 8:23 ` [PATCH 4/6] target/riscv: add check for csrs existed with U extension Weiwei Li ` (2 subsequent siblings) 5 siblings, 1 reply; 15+ messages in thread From: Weiwei Li @ 2022-07-10 8:23 UTC (permalink / raw) To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel Cc: wangjunqiang, lazyparser, Weiwei Li - line over 80 characters will trigger warning when running checkpatch Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> --- target/riscv/csr.c | 362 ++++++++++++++++++++++++--------------------- 1 file changed, 196 insertions(+), 166 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 235f2a011e..9bda1ff993 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3462,19 +3462,19 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, /* Vector CSRs */ [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_VL] = { "vl", vs, read_vl, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_VTYPE] = { "vtype", vs, read_vtype, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_VLENB] = { "vlenb", vs, read_vlenb, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + .min_priv_ver = PRIV_VERSION_1_12_0 }, /* User Timers and Counters */ [CSR_CYCLE] = { "cycle", ctr, read_hpmcounter }, [CSR_INSTRET] = { "instret", ctr, read_hpmcounter }, @@ -3493,10 +3493,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { #if !defined(CONFIG_USER_ONLY) /* Machine Timers and Counters */ - [CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, write_mhpmcounter}, - [CSR_MINSTRET] = { "minstret", any, read_hpmcounter, write_mhpmcounter}, - [CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh, write_mhpmcounterh}, - [CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh, write_mhpmcounterh}, + [CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MINSTRET] = { "minstret", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh, + write_mhpmcounterh }, + [CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh, + write_mhpmcounterh }, /* Machine Information Registers */ [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid }, @@ -3507,29 +3511,32 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, .min_priv_ver = PRIV_VERSION_1_12_0 }, /* Machine Trap Setup */ - [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL, - read_mstatus_i128 }, - [CSR_MISA] = { "misa", any, read_misa, write_misa, NULL, - read_misa_i128 }, - [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg }, - [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, - [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, - [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, - [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, - - [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, + [CSR_MSTATUS] = { "mstatus", any, read_mstatus, + write_mstatus, NULL, + read_mstatus_i128 }, + [CSR_MISA] = { "misa", any, read_misa, + write_misa, NULL, + read_misa_i128 }, + [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg }, + [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, + [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, + [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, + [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, + write_mcounteren }, + + [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, /* Machine Trap Handling */ - [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, NULL, - read_mscratch_i128, write_mscratch_i128 }, + [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, + NULL, read_mscratch_i128, write_mscratch_i128 }, [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ - [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect }, - [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg }, + [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect }, + [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg }, /* Machine-Level Interrupts (AIA) */ [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, @@ -3548,26 +3555,27 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { /* Execution environment configuration */ [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + .min_priv_ver = PRIV_VERSION_1_12_0 }, /* Supervisor Trap Setup */ - [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, - read_sstatus_i128 }, - [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie }, - [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, - [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, + [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, + NULL, read_sstatus_i128 }, + [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie }, + [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, + [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, + write_scounteren }, /* Supervisor Trap Handling */ - [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL, - read_sscratch_i128, write_sscratch_i128 }, + [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, + NULL, read_sscratch_i128, write_sscratch_i128 }, [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, @@ -3588,81 +3596,94 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph }, - [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, + write_hcounteren, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, + .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - - [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie , - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - - [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, + write_htimedelta, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, + write_htimedeltah, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + + [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, + write_vsstatus, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, + write_vsscratch, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + + [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, + .min_priv_ver = PRIV_VERSION_1_12_0 }, /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore }, - [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl }, - [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 }, - [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 }, + [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, + write_hvictl }, + [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, + write_hviprio1 }, + [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, + write_hviprio2 }, /* * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ - [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, rmw_xiselect }, - [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg }, + [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, + rmw_xiselect }, + [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg }, /* VS-Level Interrupts (H-extension with AIA) */ - [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, + [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi }, /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ - [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh }, - [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore }, + [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, + rmw_hidelegh }, + [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, + write_ignore }, [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph }, - [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h }, - [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h }, + [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, + write_hviprio1h }, + [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, + write_hviprio2h }, [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh }, [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, @@ -3697,17 +3718,26 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, /* User Pointer Masking */ - [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, - [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, - [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase }, + [CSR_UMTE] = { "umte", pointer_masking, read_umte, + write_umte }, + [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, + write_upmmask }, + [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, + write_upmbase }, /* Machine Pointer Masking */ - [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, - [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask }, - [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase }, + [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, + write_mmte }, + [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, + write_mpmmask }, + [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, + write_mpmbase }, /* Supervisor Pointer Masking */ - [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, - [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask }, - [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase }, + [CSR_SMTE] = { "smte", pointer_masking, read_smte, + write_smte }, + [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, + write_spmmask }, + [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, + write_spmbase }, /* Performance Counters */ [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter }, @@ -3740,66 +3770,66 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_hpmcounter }, [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_hpmcounter }, - [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_hpmcounter, + [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_hpmcounter, write_mhpmcounter }, - [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit, + [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit, write_mcountinhibit, .min_priv_ver = PRIV_VERSION_1_11_0 }, [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent, @@ -3891,63 +3921,63 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_hpmcounterh }, [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_hpmcounterh }, - [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh, write_mhpmcounterh }, - [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh, + [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh, write_mhpmcounterh }, #endif /* !CONFIG_USER_ONLY */ }; -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table 2022-07-10 8:23 ` [PATCH 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table Weiwei Li @ 2022-07-11 6:41 ` Alistair Francis 2022-07-11 12:41 ` Weiwei Li 0 siblings, 1 reply; 15+ messages in thread From: Alistair Francis @ 2022-07-11 6:41 UTC (permalink / raw) To: Weiwei Li Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang, Wei Wu (吴伟) On Sun, Jul 10, 2022 at 6:28 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > - line over 80 characters will trigger warning when running checkpatch > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- > target/riscv/csr.c | 362 ++++++++++++++++++++++++--------------------- > 1 file changed, 196 insertions(+), 166 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 235f2a011e..9bda1ff993 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -3462,19 +3462,19 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, > /* Vector CSRs */ > [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, Thanks for this! I think while we are changing these we should have all of the newlines start at the same position. So the .min_priv_ver should line up with "vstart" in this case Alistair > [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > [CSR_VL] = { "vl", vs, read_vl, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > [CSR_VTYPE] = { "vtype", vs, read_vtype, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > [CSR_VLENB] = { "vlenb", vs, read_vlenb, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > /* User Timers and Counters */ > [CSR_CYCLE] = { "cycle", ctr, read_hpmcounter }, > [CSR_INSTRET] = { "instret", ctr, read_hpmcounter }, > @@ -3493,10 +3493,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > > #if !defined(CONFIG_USER_ONLY) > /* Machine Timers and Counters */ > - [CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, write_mhpmcounter}, > - [CSR_MINSTRET] = { "minstret", any, read_hpmcounter, write_mhpmcounter}, > - [CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh, write_mhpmcounterh}, > - [CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh, write_mhpmcounterh}, > + [CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, > + write_mhpmcounter }, > + [CSR_MINSTRET] = { "minstret", any, read_hpmcounter, > + write_mhpmcounter }, > + [CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh, > + write_mhpmcounterh }, > + [CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh, > + write_mhpmcounterh }, > > /* Machine Information Registers */ > [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid }, > @@ -3507,29 +3511,32 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, > .min_priv_ver = PRIV_VERSION_1_12_0 }, > /* Machine Trap Setup */ > - [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL, > - read_mstatus_i128 }, > - [CSR_MISA] = { "misa", any, read_misa, write_misa, NULL, > - read_misa_i128 }, > - [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg }, > - [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, > - [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, > - [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, > - [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, > - > - [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, > + [CSR_MSTATUS] = { "mstatus", any, read_mstatus, > + write_mstatus, NULL, > + read_mstatus_i128 }, > + [CSR_MISA] = { "misa", any, read_misa, > + write_misa, NULL, > + read_misa_i128 }, > + [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg }, > + [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, > + [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, > + [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, > + [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, > + write_mcounteren }, > + > + [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, > > /* Machine Trap Handling */ > - [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, NULL, > - read_mscratch_i128, write_mscratch_i128 }, > + [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, > + NULL, read_mscratch_i128, write_mscratch_i128 }, > [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, > [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, > [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, > [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, > > /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ > - [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect }, > - [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg }, > + [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect }, > + [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg }, > > /* Machine-Level Interrupts (AIA) */ > [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, > @@ -3548,26 +3555,27 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > > /* Execution environment configuration */ > [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > /* Supervisor Trap Setup */ > - [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, > - read_sstatus_i128 }, > - [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie }, > - [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, > - [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, > + [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, > + NULL, read_sstatus_i128 }, > + [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie }, > + [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, > + [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, > + write_scounteren }, > > /* Supervisor Trap Handling */ > - [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL, > - read_sscratch_i128, write_sscratch_i128 }, > + [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, > + NULL, read_sscratch_i128, write_sscratch_i128 }, > [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, > [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, > [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, > @@ -3588,81 +3596,94 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, > [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph }, > > - [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, > + write_hcounteren, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - > - [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie , > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - > - [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, > + write_htimedelta, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, > + write_htimedeltah, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + > + [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, > + write_vsstatus, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, > + write_vsscratch, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + > + [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ > [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore }, > - [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl }, > - [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 }, > - [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 }, > + [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, > + write_hvictl }, > + [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, > + write_hviprio1 }, > + [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, > + write_hviprio2 }, > > /* > * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) > */ > - [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, rmw_xiselect }, > - [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg }, > + [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, > + rmw_xiselect }, > + [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg }, > > /* VS-Level Interrupts (H-extension with AIA) */ > - [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, > + [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, > [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi }, > > /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ > - [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh }, > - [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore }, > + [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, > + rmw_hidelegh }, > + [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, > + write_ignore }, > [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph }, > - [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h }, > - [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h }, > + [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, > + write_hviprio1h }, > + [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, > + write_hviprio2h }, > [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh }, > [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, > > @@ -3697,17 +3718,26 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, > > /* User Pointer Masking */ > - [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, > - [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, > - [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase }, > + [CSR_UMTE] = { "umte", pointer_masking, read_umte, > + write_umte }, > + [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, > + write_upmmask }, > + [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, > + write_upmbase }, > /* Machine Pointer Masking */ > - [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, > - [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask }, > - [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase }, > + [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, > + write_mmte }, > + [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, > + write_mpmmask }, > + [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, > + write_mpmbase }, > /* Supervisor Pointer Masking */ > - [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, > - [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask }, > - [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase }, > + [CSR_SMTE] = { "smte", pointer_masking, read_smte, > + write_smte }, > + [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, > + write_spmmask }, > + [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, > + write_spmbase }, > > /* Performance Counters */ > [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter }, > @@ -3740,66 +3770,66 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_hpmcounter }, > [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_hpmcounter }, > > - [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_hpmcounter, > write_mhpmcounter }, > - [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_hpmcounter, > + [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_hpmcounter, > write_mhpmcounter }, > > - [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit, > + [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit, > write_mcountinhibit, .min_priv_ver = PRIV_VERSION_1_11_0 }, > > [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent, > @@ -3891,63 +3921,63 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_hpmcounterh }, > [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_hpmcounterh }, > > - [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > - [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh, > + [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh, > write_mhpmcounterh }, > #endif /* !CONFIG_USER_ONLY */ > }; > -- > 2.17.1 > > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table 2022-07-11 6:41 ` Alistair Francis @ 2022-07-11 12:41 ` Weiwei Li 0 siblings, 0 replies; 15+ messages in thread From: Weiwei Li @ 2022-07-11 12:41 UTC (permalink / raw) To: Alistair Francis Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang, Wei Wu (吴伟) 在 2022/7/11 下午2:41, Alistair Francis 写道: > On Sun, Jul 10, 2022 at 6:28 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: >> - line over 80 characters will trigger warning when running checkpatch >> >> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> >> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> >> --- >> target/riscv/csr.c | 362 ++++++++++++++++++++++++--------------------- >> 1 file changed, 196 insertions(+), 166 deletions(-) >> >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c >> index 235f2a011e..9bda1ff993 100644 >> --- a/target/riscv/csr.c >> +++ b/target/riscv/csr.c >> @@ -3462,19 +3462,19 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { >> [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, >> /* Vector CSRs */ >> [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, > Thanks for this! > > I think while we are changing these we should have all of the newlines > start at the same position. So the .min_priv_ver should line up with > "vstart" in this case > > Alistair OK. I'll do this later. Regards, Weiwei Li >> [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> [CSR_VL] = { "vl", vs, read_vl, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> [CSR_VTYPE] = { "vtype", vs, read_vtype, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> [CSR_VLENB] = { "vlenb", vs, read_vlenb, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> /* User Timers and Counters */ >> [CSR_CYCLE] = { "cycle", ctr, read_hpmcounter }, >> [CSR_INSTRET] = { "instret", ctr, read_hpmcounter }, >> @@ -3493,10 +3493,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { >> >> #if !defined(CONFIG_USER_ONLY) >> /* Machine Timers and Counters */ >> - [CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, write_mhpmcounter}, >> - [CSR_MINSTRET] = { "minstret", any, read_hpmcounter, write_mhpmcounter}, >> - [CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh, write_mhpmcounterh}, >> - [CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh, write_mhpmcounterh}, >> + [CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, >> + write_mhpmcounter }, >> + [CSR_MINSTRET] = { "minstret", any, read_hpmcounter, >> + write_mhpmcounter }, >> + [CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh, >> + write_mhpmcounterh }, >> + [CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh, >> + write_mhpmcounterh }, >> >> /* Machine Information Registers */ >> [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid }, >> @@ -3507,29 +3511,32 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { >> [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, >> .min_priv_ver = PRIV_VERSION_1_12_0 }, >> /* Machine Trap Setup */ >> - [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL, >> - read_mstatus_i128 }, >> - [CSR_MISA] = { "misa", any, read_misa, write_misa, NULL, >> - read_misa_i128 }, >> - [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg }, >> - [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, >> - [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, >> - [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, >> - [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, >> - >> - [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, >> + [CSR_MSTATUS] = { "mstatus", any, read_mstatus, >> + write_mstatus, NULL, >> + read_mstatus_i128 }, >> + [CSR_MISA] = { "misa", any, read_misa, >> + write_misa, NULL, >> + read_misa_i128 }, >> + [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg }, >> + [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, >> + [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, >> + [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, >> + [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, >> + write_mcounteren }, >> + >> + [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, >> >> /* Machine Trap Handling */ >> - [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, NULL, >> - read_mscratch_i128, write_mscratch_i128 }, >> + [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, >> + NULL, read_mscratch_i128, write_mscratch_i128 }, >> [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, >> [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, >> [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, >> [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, >> >> /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ >> - [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect }, >> - [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg }, >> + [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect }, >> + [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg }, >> >> /* Machine-Level Interrupts (AIA) */ >> [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, >> @@ -3548,26 +3555,27 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { >> >> /* Execution environment configuration */ >> [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> >> /* Supervisor Trap Setup */ >> - [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, >> - read_sstatus_i128 }, >> - [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie }, >> - [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, >> - [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, >> + [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, >> + NULL, read_sstatus_i128 }, >> + [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie }, >> + [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, >> + [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, >> + write_scounteren }, >> >> /* Supervisor Trap Handling */ >> - [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL, >> - read_sscratch_i128, write_sscratch_i128 }, >> + [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, >> + NULL, read_sscratch_i128, write_sscratch_i128 }, >> [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, >> [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, >> [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, >> @@ -3588,81 +3596,94 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { >> [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, >> [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph }, >> >> - [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, >> + write_hcounteren, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - >> - [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie , >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - >> - [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> - [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, >> - .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, >> + write_htimedelta, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, >> + write_htimedeltah, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + >> + [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, >> + write_vsstatus, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, >> + write_vsscratch, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + >> + [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> + [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, >> + .min_priv_ver = PRIV_VERSION_1_12_0 }, >> >> /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ >> [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore }, >> - [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl }, >> - [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 }, >> - [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 }, >> + [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, >> + write_hvictl }, >> + [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, >> + write_hviprio1 }, >> + [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, >> + write_hviprio2 }, >> >> /* >> * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) >> */ >> - [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, rmw_xiselect }, >> - [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg }, >> + [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, >> + rmw_xiselect }, >> + [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg }, >> >> /* VS-Level Interrupts (H-extension with AIA) */ >> - [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, >> + [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, >> [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi }, >> >> /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ >> - [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh }, >> - [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore }, >> + [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, >> + rmw_hidelegh }, >> + [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, >> + write_ignore }, >> [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph }, >> - [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h }, >> - [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h }, >> + [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, >> + write_hviprio1h }, >> + [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, >> + write_hviprio2h }, >> [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh }, >> [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, >> >> @@ -3697,17 +3718,26 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { >> [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, >> >> /* User Pointer Masking */ >> - [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, >> - [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, >> - [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase }, >> + [CSR_UMTE] = { "umte", pointer_masking, read_umte, >> + write_umte }, >> + [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, >> + write_upmmask }, >> + [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, >> + write_upmbase }, >> /* Machine Pointer Masking */ >> - [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, >> - [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask }, >> - [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase }, >> + [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, >> + write_mmte }, >> + [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, >> + write_mpmmask }, >> + [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, >> + write_mpmbase }, >> /* Supervisor Pointer Masking */ >> - [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, >> - [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask }, >> - [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase }, >> + [CSR_SMTE] = { "smte", pointer_masking, read_smte, >> + write_smte }, >> + [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, >> + write_spmmask }, >> + [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, >> + write_spmbase }, >> >> /* Performance Counters */ >> [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter }, >> @@ -3740,66 +3770,66 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { >> [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_hpmcounter }, >> [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_hpmcounter }, >> >> - [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_hpmcounter, >> write_mhpmcounter }, >> - [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_hpmcounter, >> + [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_hpmcounter, >> write_mhpmcounter }, >> >> - [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit, >> + [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit, >> write_mcountinhibit, .min_priv_ver = PRIV_VERSION_1_11_0 }, >> >> [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent, >> @@ -3891,63 +3921,63 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { >> [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_hpmcounterh }, >> [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_hpmcounterh }, >> >> - [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> - [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh, >> + [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh, >> write_mhpmcounterh }, >> #endif /* !CONFIG_USER_ONLY */ >> }; >> -- >> 2.17.1 >> >> ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 4/6] target/riscv: add check for csrs existed with U extension 2022-07-10 8:23 [PATCH 0/6] Improve the U/S/H extension related check Weiwei Li ` (2 preceding siblings ...) 2022-07-10 8:23 ` [PATCH 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table Weiwei Li @ 2022-07-10 8:23 ` Weiwei Li 2022-07-11 6:42 ` Alistair Francis 2022-07-10 8:23 ` [PATCH 5/6] target/riscv: fix checks in hmode/hmode32 Weiwei Li 2022-07-10 8:24 ` [PATCH 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check Weiwei Li 5 siblings, 1 reply; 15+ messages in thread From: Weiwei Li @ 2022-07-10 8:23 UTC (permalink / raw) To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel Cc: wangjunqiang, lazyparser, Weiwei Li - add umode/umode32 predicate for mcounteren,menvcfg/menvcfgh Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> --- target/riscv/csr.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9bda1ff993..0d8e98b7a9 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -339,6 +339,25 @@ static RISCVException hmode32(CPURISCVState *env, int csrno) } +static RISCVException umode(CPURISCVState *env, int csrno) +{ + if (riscv_has_ext(env, RVU)) { + /* User extension is supported */ + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} + +static RISCVException umode32(CPURISCVState *env, int csrno) +{ + if (riscv_cpu_mxl(env) != MXL_RV32) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return umode(env, csrno); +} + /* Checks if PointerMasking registers could be accessed */ static RISCVException pointer_masking(CPURISCVState *env, int csrno) { @@ -3521,7 +3540,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, - [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, + [CSR_MCOUNTEREN] = { "mcounteren", umode, read_mcounteren, write_mcounteren }, [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, @@ -3554,9 +3573,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, /* Execution environment configuration */ - [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg, + [CSR_MENVCFG] = { "menvcfg", umode, read_menvcfg, write_menvcfg, .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, + [CSR_MENVCFGH] = { "menvcfgh", umode32, read_menvcfgh, write_menvcfgh, .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, .min_priv_ver = PRIV_VERSION_1_12_0 }, -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 4/6] target/riscv: add check for csrs existed with U extension 2022-07-10 8:23 ` [PATCH 4/6] target/riscv: add check for csrs existed with U extension Weiwei Li @ 2022-07-11 6:42 ` Alistair Francis 0 siblings, 0 replies; 15+ messages in thread From: Alistair Francis @ 2022-07-11 6:42 UTC (permalink / raw) To: Weiwei Li Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang, Wei Wu (吴伟) On Sun, Jul 10, 2022 at 6:28 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > - add umode/umode32 predicate for mcounteren,menvcfg/menvcfgh > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/csr.c | 25 ++++++++++++++++++++++--- > 1 file changed, 22 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 9bda1ff993..0d8e98b7a9 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -339,6 +339,25 @@ static RISCVException hmode32(CPURISCVState *env, int csrno) > > } > > +static RISCVException umode(CPURISCVState *env, int csrno) > +{ > + if (riscv_has_ext(env, RVU)) { > + /* User extension is supported */ > + return RISCV_EXCP_NONE; > + } > + > + return RISCV_EXCP_ILLEGAL_INST; > +} > + > +static RISCVException umode32(CPURISCVState *env, int csrno) > +{ > + if (riscv_cpu_mxl(env) != MXL_RV32) { > + return RISCV_EXCP_ILLEGAL_INST; > + } > + > + return umode(env, csrno); > +} > + > /* Checks if PointerMasking registers could be accessed */ > static RISCVException pointer_masking(CPURISCVState *env, int csrno) > { > @@ -3521,7 +3540,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, > [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, > [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, > - [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, > + [CSR_MCOUNTEREN] = { "mcounteren", umode, read_mcounteren, > write_mcounteren }, > > [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, > @@ -3554,9 +3573,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, > > /* Execution environment configuration */ > - [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg, > + [CSR_MENVCFG] = { "menvcfg", umode, read_menvcfg, write_menvcfg, > .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, > + [CSR_MENVCFGH] = { "menvcfgh", umode32, read_menvcfgh, write_menvcfgh, > .min_priv_ver = PRIV_VERSION_1_12_0 }, > [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, > .min_priv_ver = PRIV_VERSION_1_12_0 }, > -- > 2.17.1 > > ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 5/6] target/riscv: fix checks in hmode/hmode32 2022-07-10 8:23 [PATCH 0/6] Improve the U/S/H extension related check Weiwei Li ` (3 preceding siblings ...) 2022-07-10 8:23 ` [PATCH 4/6] target/riscv: add check for csrs existed with U extension Weiwei Li @ 2022-07-10 8:23 ` Weiwei Li 2022-07-11 6:46 ` Alistair Francis 2022-07-10 8:24 ` [PATCH 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check Weiwei Li 5 siblings, 1 reply; 15+ messages in thread From: Weiwei Li @ 2022-07-10 8:23 UTC (permalink / raw) To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel Cc: wangjunqiang, lazyparser, Weiwei Li - It seems that there is no explicitly description about whether the Hypervisor CSRs requires S extension - Csrs only existed in RV32 will not trigger virtual instruction fault when not in RV32 Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> --- target/riscv/csr.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0d8e98b7a9..975007f1ac 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -311,8 +311,7 @@ static int aia_smode32(CPURISCVState *env, int csrno) static RISCVException hmode(CPURISCVState *env, int csrno) { - if (riscv_has_ext(env, RVS) && - riscv_has_ext(env, RVH)) { + if (riscv_has_ext(env, RVH)) { /* Hypervisor extension is supported */ if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || env->priv == PRV_M) { @@ -328,11 +327,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno) static RISCVException hmode32(CPURISCVState *env, int csrno) { if (riscv_cpu_mxl(env) != MXL_RV32) { - if (!riscv_cpu_virt_enabled(env)) { - return RISCV_EXCP_ILLEGAL_INST; - } else { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } + return RISCV_EXCP_ILLEGAL_INST; } return hmode(env, csrno); -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 5/6] target/riscv: fix checks in hmode/hmode32 2022-07-10 8:23 ` [PATCH 5/6] target/riscv: fix checks in hmode/hmode32 Weiwei Li @ 2022-07-11 6:46 ` Alistair Francis 2022-07-11 12:45 ` Weiwei Li 0 siblings, 1 reply; 15+ messages in thread From: Alistair Francis @ 2022-07-11 6:46 UTC (permalink / raw) To: Weiwei Li Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang, Wei Wu (吴伟) On Sun, Jul 10, 2022 at 6:24 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > - It seems that there is no explicitly description about whether > the Hypervisor CSRs requires S extension > - Csrs only existed in RV32 will not trigger virtual instruction fault > when not in RV32 > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- > target/riscv/csr.c | 9 ++------- > 1 file changed, 2 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 0d8e98b7a9..975007f1ac 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -311,8 +311,7 @@ static int aia_smode32(CPURISCVState *env, int csrno) > > static RISCVException hmode(CPURISCVState *env, int csrno) > { > - if (riscv_has_ext(env, RVS) && > - riscv_has_ext(env, RVH)) { > + if (riscv_has_ext(env, RVH)) { This doesn't seem right. The spec doesn't explicitly say this, but I don't see how you can have the Hypervisor extension without S-mode > /* Hypervisor extension is supported */ > if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || > env->priv == PRV_M) { > @@ -328,11 +327,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno) > static RISCVException hmode32(CPURISCVState *env, int csrno) > { > if (riscv_cpu_mxl(env) != MXL_RV32) { > - if (!riscv_cpu_virt_enabled(env)) { > - return RISCV_EXCP_ILLEGAL_INST; > - } else { > - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; > - } > + return RISCV_EXCP_ILLEGAL_INST; Good catch Alistair > } > > return hmode(env, csrno); > -- > 2.17.1 > > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 5/6] target/riscv: fix checks in hmode/hmode32 2022-07-11 6:46 ` Alistair Francis @ 2022-07-11 12:45 ` Weiwei Li 0 siblings, 0 replies; 15+ messages in thread From: Weiwei Li @ 2022-07-11 12:45 UTC (permalink / raw) To: Alistair Francis Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang, Wei Wu (吴伟) 在 2022/7/11 下午2:46, Alistair Francis 写道: > On Sun, Jul 10, 2022 at 6:24 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: >> - It seems that there is no explicitly description about whether >> the Hypervisor CSRs requires S extension >> - Csrs only existed in RV32 will not trigger virtual instruction fault >> when not in RV32 >> >> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> >> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> >> --- >> target/riscv/csr.c | 9 ++------- >> 1 file changed, 2 insertions(+), 7 deletions(-) >> >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c >> index 0d8e98b7a9..975007f1ac 100644 >> --- a/target/riscv/csr.c >> +++ b/target/riscv/csr.c >> @@ -311,8 +311,7 @@ static int aia_smode32(CPURISCVState *env, int csrno) >> >> static RISCVException hmode(CPURISCVState *env, int csrno) >> { >> - if (riscv_has_ext(env, RVS) && >> - riscv_has_ext(env, RVH)) { >> + if (riscv_has_ext(env, RVH)) { > This doesn't seem right. The spec doesn't explicitly say this, but I > don't see how you can have the Hypervisor extension without S-mode I'm also wonder about this. However, if H extension implicitly requires S-mode, maybe it's better to add a check for this in riscv_cpu_realize, and we just check H here. Regards, Weiwei Li > >> /* Hypervisor extension is supported */ >> if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || >> env->priv == PRV_M) { >> @@ -328,11 +327,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno) >> static RISCVException hmode32(CPURISCVState *env, int csrno) >> { >> if (riscv_cpu_mxl(env) != MXL_RV32) { >> - if (!riscv_cpu_virt_enabled(env)) { >> - return RISCV_EXCP_ILLEGAL_INST; >> - } else { >> - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; >> - } >> + return RISCV_EXCP_ILLEGAL_INST; > Good catch > > Alistair > >> } >> >> return hmode(env, csrno); >> -- >> 2.17.1 >> >> ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check 2022-07-10 8:23 [PATCH 0/6] Improve the U/S/H extension related check Weiwei Li ` (4 preceding siblings ...) 2022-07-10 8:23 ` [PATCH 5/6] target/riscv: fix checks in hmode/hmode32 Weiwei Li @ 2022-07-10 8:24 ` Weiwei Li 2022-07-11 6:49 ` Alistair Francis 5 siblings, 1 reply; 15+ messages in thread From: Weiwei Li @ 2022-07-10 8:24 UTC (permalink / raw) To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel Cc: wangjunqiang, lazyparser, Weiwei Li Just add 1 to the effective privledge level when in HS mode, then reuse the check 'effective_priv < csr_priv' in riscv_csrrw_check to replace the privilege level related check in hmode. Then, hmode will only check whether H extension is supported. when accessing Hypervior CSRs: 1) if access from M privilege level, the check of 'effective_priv < csr_priv' passes, returns hmode(...) which will return RISCV_EXCP_ILLEGAL_INST when H extension is not supported and return RISCV_EXCP_NONE otherwise. 2) if access from HS privilege level, effective_priv will add 1, the check passes too, also returns hmode(...) too. 3) if access from VS/VU privilege level, the check fails, and returns RISCV_EXCP_VIRT_INSTRUCTION_FAULT 4) if access from U privilege level, the check fails, and returns RISCV_EXCP_ILLEGAL_INST Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> --- target/riscv/csr.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 975007f1ac..2b3ed94366 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -312,13 +312,7 @@ static int aia_smode32(CPURISCVState *env, int csrno) static RISCVException hmode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVH)) { - /* Hypervisor extension is supported */ - if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || - env->priv == PRV_M) { - return RISCV_EXCP_NONE; - } else { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } + return RISCV_EXCP_NONE; } return RISCV_EXCP_ILLEGAL_INST; @@ -3280,13 +3274,11 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, #if !defined(CONFIG_USER_ONLY) int csr_priv, effective_priv = env->priv; - if (riscv_has_ext(env, RVH) && env->priv == PRV_S) { + if (riscv_has_ext(env, RVH) && env->priv == PRV_S && + !riscv_cpu_virt_enabled(env)) { /* - * We are in either HS or VS mode. - * Add 1 to the effective privledge level to allow us to access the - * Hypervisor CSRs. The `hmode` predicate will determine if access - * should be allowed(HS) or if a virtual instruction exception should be - * raised(VS). + * We are in HS mode. Add 1 to the effective privledge level to + * allow us to access the Hypervisor CSRs. */ effective_priv++; } -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check 2022-07-10 8:24 ` [PATCH 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check Weiwei Li @ 2022-07-11 6:49 ` Alistair Francis 0 siblings, 0 replies; 15+ messages in thread From: Alistair Francis @ 2022-07-11 6:49 UTC (permalink / raw) To: Weiwei Li Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V, qemu-devel@nongnu.org Developers, wangjunqiang, Wei Wu (吴伟) On Sun, Jul 10, 2022 at 6:30 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > Just add 1 to the effective privledge level when in HS mode, then reuse the check > 'effective_priv < csr_priv' in riscv_csrrw_check to replace the privilege level > related check in hmode. Then, hmode will only check whether H extension is supported. > > when accessing Hypervior CSRs: > 1) if access from M privilege level, the check of 'effective_priv < csr_priv' > passes, returns hmode(...) which will return RISCV_EXCP_ILLEGAL_INST when H > extension is not supported and return RISCV_EXCP_NONE otherwise. > 2) if access from HS privilege level, effective_priv will add 1, the check > passes too, also returns hmode(...) too. > 3) if access from VS/VU privilege level, the check fails, and returns > RISCV_EXCP_VIRT_INSTRUCTION_FAULT > 4) if access from U privilege level, the check fails, and returns > RISCV_EXCP_ILLEGAL_INST > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/csr.c | 18 +++++------------- > 1 file changed, 5 insertions(+), 13 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 975007f1ac..2b3ed94366 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -312,13 +312,7 @@ static int aia_smode32(CPURISCVState *env, int csrno) > static RISCVException hmode(CPURISCVState *env, int csrno) > { > if (riscv_has_ext(env, RVH)) { > - /* Hypervisor extension is supported */ > - if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || > - env->priv == PRV_M) { > - return RISCV_EXCP_NONE; > - } else { > - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; > - } > + return RISCV_EXCP_NONE; > } > > return RISCV_EXCP_ILLEGAL_INST; > @@ -3280,13 +3274,11 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, > #if !defined(CONFIG_USER_ONLY) > int csr_priv, effective_priv = env->priv; > > - if (riscv_has_ext(env, RVH) && env->priv == PRV_S) { > + if (riscv_has_ext(env, RVH) && env->priv == PRV_S && > + !riscv_cpu_virt_enabled(env)) { > /* > - * We are in either HS or VS mode. > - * Add 1 to the effective privledge level to allow us to access the > - * Hypervisor CSRs. The `hmode` predicate will determine if access > - * should be allowed(HS) or if a virtual instruction exception should be > - * raised(VS). > + * We are in HS mode. Add 1 to the effective privledge level to > + * allow us to access the Hypervisor CSRs. > */ > effective_priv++; > } > -- > 2.17.1 > > ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2022-07-11 12:47 UTC | newest] Thread overview: 15+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-07-10 8:23 [PATCH 0/6] Improve the U/S/H extension related check Weiwei Li 2022-07-10 8:23 ` [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations Weiwei Li 2022-07-11 5:29 ` Alistair Francis 2022-07-10 8:23 ` [PATCH 2/6] target/riscv: H extension depends on I extension Weiwei Li 2022-07-11 5:29 ` Alistair Francis 2022-07-10 8:23 ` [PATCH 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table Weiwei Li 2022-07-11 6:41 ` Alistair Francis 2022-07-11 12:41 ` Weiwei Li 2022-07-10 8:23 ` [PATCH 4/6] target/riscv: add check for csrs existed with U extension Weiwei Li 2022-07-11 6:42 ` Alistair Francis 2022-07-10 8:23 ` [PATCH 5/6] target/riscv: fix checks in hmode/hmode32 Weiwei Li 2022-07-11 6:46 ` Alistair Francis 2022-07-11 12:45 ` Weiwei Li 2022-07-10 8:24 ` [PATCH 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check Weiwei Li 2022-07-11 6:49 ` Alistair Francis
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