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Iglesias" Content-Type: text/plain; charset="UTF-8" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::141 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, Peter Maydell , Edgar Iglesias , Sai Pavan Boddu , Francisco Iglesias , Alistair Francis , Richard Henderson , "qemu-devel@nongnu.org Developers" , KONRAD Frederic , Stefano Stabellini , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Luc Michel Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, Apr 17, 2020 at 12:12 PM Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > Add the opcode-0x0-illegal CPU property to control if the core > should trap opcode zero as illegal. > > Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Alistair > --- > target/microblaze/cpu.c | 6 +++++- > target/microblaze/cpu.h | 1 + > target/microblaze/translate.c | 2 +- > 3 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c > index a2c2f271df..1044120702 100644 > --- a/target/microblaze/cpu.c > +++ b/target/microblaze/cpu.c > @@ -206,7 +206,9 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) > (cpu->cfg.dopb_bus_exception ? > PVR2_DOPB_BUS_EXC_MASK : 0) | > (cpu->cfg.iopb_bus_exception ? > - PVR2_IOPB_BUS_EXC_MASK : 0); > + PVR2_IOPB_BUS_EXC_MASK : 0) | > + (cpu->cfg.opcode_0_illegal ? > + PVR2_OPCODE_0x0_ILL_MASK : 0); > > env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? > PVR5_DCACHE_WRITEBACK_MASK : 0; > @@ -274,6 +276,8 @@ static Property mb_properties[] = { > /* Enables bus exceptions on failed instruction fetches. */ > DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU, > cfg.iopb_bus_exception, false), > + DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU, > + cfg.opcode_0_illegal, false), > DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), > DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), > DEFINE_PROP_END_OF_LIST(), > diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h > index 1a700a880c..d51587b342 100644 > --- a/target/microblaze/cpu.h > +++ b/target/microblaze/cpu.h > @@ -303,6 +303,7 @@ struct MicroBlazeCPU { > bool endi; > bool dopb_bus_exception; > bool iopb_bus_exception; > + bool opcode_0_illegal; > char *version; > uint8_t pvr; > } cfg; > diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c > index 37a844db99..222632b670 100644 > --- a/target/microblaze/translate.c > +++ b/target/microblaze/translate.c > @@ -1573,7 +1573,7 @@ static inline void decode(DisasContext *dc, uint32_t ir) > LOG_DIS("%8.8x\t", dc->ir); > > if (ir == 0) { > - trap_illegal(dc, dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK); > + trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal); > /* Don't decode nop/zero instructions any further. */ > return; > } > -- > 2.20.1 > >