* [PATCH v3 2/2] hw/riscv/riscv-iommu-bits: Remove duplicate definitions
2025-01-15 14:17 [PATCH v3 1/2] hw/riscv/riscv-iommu: Remove redundant struct members Jason Chien
@ 2025-01-15 14:17 ` Jason Chien
2025-01-31 0:23 ` Alistair Francis
2025-01-22 8:10 ` [PATCH v3 1/2] hw/riscv/riscv-iommu: Remove redundant struct members Jason Chien
2025-01-31 0:22 ` Alistair Francis
2 siblings, 1 reply; 6+ messages in thread
From: Jason Chien @ 2025-01-15 14:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Jason Chien, Andrew Jones
The header contains duplicate macro definitions.
This commit eliminates the duplicate part.
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
hw/riscv/riscv-iommu-bits.h | 22 ++++++----------------
1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h
index 485f36b9c9..de599b80d6 100644
--- a/hw/riscv/riscv-iommu-bits.h
+++ b/hw/riscv/riscv-iommu-bits.h
@@ -50,8 +50,14 @@ struct riscv_iommu_pq_record {
#define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33)
#define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34)
#define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40)
+
/* Payload fields */
+#define RISCV_IOMMU_PREQ_PAYLOAD_R BIT_ULL(0)
+#define RISCV_IOMMU_PREQ_PAYLOAD_W BIT_ULL(1)
+#define RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2)
#define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0)
+#define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3)
+#define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12)
/* Common field positions */
#define RISCV_IOMMU_PPN_FIELD GENMASK_ULL(53, 10)
@@ -382,22 +388,6 @@ enum riscv_iommu_fq_ttypes {
RISCV_IOMMU_FW_TTYPE_PCIE_MSG_REQ = 9,
};
-/* Header fields */
-#define RISCV_IOMMU_PREQ_HDR_PID GENMASK_ULL(31, 12)
-#define RISCV_IOMMU_PREQ_HDR_PV BIT_ULL(32)
-#define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33)
-#define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34)
-#define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40)
-
-/* Payload fields */
-#define RISCV_IOMMU_PREQ_PAYLOAD_R BIT_ULL(0)
-#define RISCV_IOMMU_PREQ_PAYLOAD_W BIT_ULL(1)
-#define RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2)
-#define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0)
-#define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3)
-#define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12)
-
-
/*
* struct riscv_iommu_msi_pte - MSI Page Table Entry
*/
--
2.43.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v3 2/2] hw/riscv/riscv-iommu-bits: Remove duplicate definitions
2025-01-15 14:17 ` [PATCH v3 2/2] hw/riscv/riscv-iommu-bits: Remove duplicate definitions Jason Chien
@ 2025-01-31 0:23 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2025-01-31 0:23 UTC (permalink / raw)
To: Jason Chien
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Andrew Jones
On Thu, Jan 16, 2025 at 12:18 AM Jason Chien <jason.chien@sifive.com> wrote:
>
> The header contains duplicate macro definitions.
> This commit eliminates the duplicate part.
>
> Signed-off-by: Jason Chien <jason.chien@sifive.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/riscv-iommu-bits.h | 22 ++++++----------------
> 1 file changed, 6 insertions(+), 16 deletions(-)
>
> diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h
> index 485f36b9c9..de599b80d6 100644
> --- a/hw/riscv/riscv-iommu-bits.h
> +++ b/hw/riscv/riscv-iommu-bits.h
> @@ -50,8 +50,14 @@ struct riscv_iommu_pq_record {
> #define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33)
> #define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34)
> #define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40)
> +
> /* Payload fields */
> +#define RISCV_IOMMU_PREQ_PAYLOAD_R BIT_ULL(0)
> +#define RISCV_IOMMU_PREQ_PAYLOAD_W BIT_ULL(1)
> +#define RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2)
> #define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0)
> +#define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3)
> +#define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12)
>
> /* Common field positions */
> #define RISCV_IOMMU_PPN_FIELD GENMASK_ULL(53, 10)
> @@ -382,22 +388,6 @@ enum riscv_iommu_fq_ttypes {
> RISCV_IOMMU_FW_TTYPE_PCIE_MSG_REQ = 9,
> };
>
> -/* Header fields */
> -#define RISCV_IOMMU_PREQ_HDR_PID GENMASK_ULL(31, 12)
> -#define RISCV_IOMMU_PREQ_HDR_PV BIT_ULL(32)
> -#define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33)
> -#define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34)
> -#define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40)
> -
> -/* Payload fields */
> -#define RISCV_IOMMU_PREQ_PAYLOAD_R BIT_ULL(0)
> -#define RISCV_IOMMU_PREQ_PAYLOAD_W BIT_ULL(1)
> -#define RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2)
> -#define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0)
> -#define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3)
> -#define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12)
> -
> -
> /*
> * struct riscv_iommu_msi_pte - MSI Page Table Entry
> */
> --
> 2.43.2
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3 1/2] hw/riscv/riscv-iommu: Remove redundant struct members
2025-01-15 14:17 [PATCH v3 1/2] hw/riscv/riscv-iommu: Remove redundant struct members Jason Chien
2025-01-15 14:17 ` [PATCH v3 2/2] hw/riscv/riscv-iommu-bits: Remove duplicate definitions Jason Chien
@ 2025-01-22 8:10 ` Jason Chien
2025-01-31 0:30 ` Alistair Francis
2025-01-31 0:22 ` Alistair Francis
2 siblings, 1 reply; 6+ messages in thread
From: Jason Chien @ 2025-01-22 8:10 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Andrew Jones
[-- Attachment #1: Type: text/plain, Size: 1327 bytes --]
Ping
Jason Chien <jason.chien@sifive.com> 於 2025年1月15日 週三 下午10:17寫道：
> Initially, the IOMMU would create a thread, but this thread was removed in
> the merged version. The struct members for thread control should have been
> removed as well, but they were not removed in commit 0c54acb8243
> ("hw/riscv: add RISC-V IOMMU base emulation").
>
> Signed-off-by: Jason Chien <jason.chien@sifive.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
> hw/riscv/riscv-iommu.h | 5 -----
> 1 file changed, 5 deletions(-)
>
> diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
> index 9424989df4..fa8a50fa24 100644
> --- a/hw/riscv/riscv-iommu.h
> +++ b/hw/riscv/riscv-iommu.h
> @@ -58,11 +58,6 @@ struct RISCVIOMMUState {
> /* interrupt notifier */
> void (*notify)(RISCVIOMMUState *iommu, unsigned vector);
>
> - /* IOMMU State Machine */
> - QemuThread core_proc; /* Background processing thread */
> - QemuCond core_cond; /* Background processing wake up signal */
> - unsigned core_exec; /* Processing thread execution actions */
> -
> /* IOMMU target address space */
> AddressSpace *target_as;
> MemoryRegion *target_mr;
> --
> 2.43.2
>
>
[-- Attachment #2: Type: text/html, Size: 1932 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v3 1/2] hw/riscv/riscv-iommu: Remove redundant struct members
2025-01-22 8:10 ` [PATCH v3 1/2] hw/riscv/riscv-iommu: Remove redundant struct members Jason Chien
@ 2025-01-31 0:30 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2025-01-31 0:30 UTC (permalink / raw)
To: Jason Chien
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Andrew Jones
On Wed, Jan 22, 2025 at 6:11 PM Jason Chien <jason.chien@sifive.com> wrote:
>
> Ping
>
> Jason Chien <jason.chien@sifive.com> 於 2025年1月15日 週三 下午10:17寫道：
>>
>> Initially, the IOMMU would create a thread, but this thread was removed in
>> the merged version. The struct members for thread control should have been
>> removed as well, but they were not removed in commit 0c54acb8243
>> ("hw/riscv: add RISC-V IOMMU base emulation").
>>
>> Signed-off-by: Jason Chien <jason.chien@sifive.com>
>> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Please use a cover letter for multiple patches in the future:
https://www.qemu.org/docs/master/devel/submitting-a-patch.html#include-a-meaningful-cover-letter
Thanks!
Applied to riscv-to-apply.next
Alistair
>> ---
>> hw/riscv/riscv-iommu.h | 5 -----
>> 1 file changed, 5 deletions(-)
>>
>> diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
>> index 9424989df4..fa8a50fa24 100644
>> --- a/hw/riscv/riscv-iommu.h
>> +++ b/hw/riscv/riscv-iommu.h
>> @@ -58,11 +58,6 @@ struct RISCVIOMMUState {
>> /* interrupt notifier */
>> void (*notify)(RISCVIOMMUState *iommu, unsigned vector);
>>
>> - /* IOMMU State Machine */
>> - QemuThread core_proc; /* Background processing thread */
>> - QemuCond core_cond; /* Background processing wake up signal */
>> - unsigned core_exec; /* Processing thread execution actions */
>> -
>> /* IOMMU target address space */
>> AddressSpace *target_as;
>> MemoryRegion *target_mr;
>> --
>> 2.43.2
>>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3 1/2] hw/riscv/riscv-iommu: Remove redundant struct members
2025-01-15 14:17 [PATCH v3 1/2] hw/riscv/riscv-iommu: Remove redundant struct members Jason Chien
2025-01-15 14:17 ` [PATCH v3 2/2] hw/riscv/riscv-iommu-bits: Remove duplicate definitions Jason Chien
2025-01-22 8:10 ` [PATCH v3 1/2] hw/riscv/riscv-iommu: Remove redundant struct members Jason Chien
@ 2025-01-31 0:22 ` Alistair Francis
2 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2025-01-31 0:22 UTC (permalink / raw)
To: Jason Chien
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Andrew Jones
On Thu, Jan 16, 2025 at 12:19 AM Jason Chien <jason.chien@sifive.com> wrote:
>
> Initially, the IOMMU would create a thread, but this thread was removed in
> the merged version. The struct members for thread control should have been
> removed as well, but they were not removed in commit 0c54acb8243
> ("hw/riscv: add RISC-V IOMMU base emulation").
>
> Signed-off-by: Jason Chien <jason.chien@sifive.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/riscv-iommu.h | 5 -----
> 1 file changed, 5 deletions(-)
>
> diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
> index 9424989df4..fa8a50fa24 100644
> --- a/hw/riscv/riscv-iommu.h
> +++ b/hw/riscv/riscv-iommu.h
> @@ -58,11 +58,6 @@ struct RISCVIOMMUState {
> /* interrupt notifier */
> void (*notify)(RISCVIOMMUState *iommu, unsigned vector);
>
> - /* IOMMU State Machine */
> - QemuThread core_proc; /* Background processing thread */
> - QemuCond core_cond; /* Background processing wake up signal */
> - unsigned core_exec; /* Processing thread execution actions */
> -
> /* IOMMU target address space */
> AddressSpace *target_as;
> MemoryRegion *target_mr;
> --
> 2.43.2
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread