* [PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
@ 2023-03-30 3:46 Weiwei Li
2023-03-30 11:13 ` Daniel Henrique Barboza
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Weiwei Li @ 2023-03-30 3:46 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
decode_save_opc() will not work for generate_exception(), since 0 is passed
to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
not be restored in this case.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/insn_trans/trans_rvh.c.inc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index 9248b48c36..4b730cd492 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -20,6 +20,8 @@
static bool check_access(DisasContext *ctx)
{
if (!ctx->hlsx) {
+ tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
+ offsetof(CPURISCVState, bins));
if (ctx->virt_enabled) {
generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
} else {
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
2023-03-30 3:46 [PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault Weiwei Li
@ 2023-03-30 11:13 ` Daniel Henrique Barboza
2023-04-05 3:55 ` Alistair Francis
2023-04-05 6:43 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Daniel Henrique Barboza @ 2023-03-30 11:13 UTC (permalink / raw)
To: Weiwei Li, qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, zhiwei_liu, wangjunqiang,
lazyparser
On 3/30/23 00:46, Weiwei Li wrote:
> decode_save_opc() will not work for generate_exception(), since 0 is passed
> to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
> not be restored in this case.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/insn_trans/trans_rvh.c.inc | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
> index 9248b48c36..4b730cd492 100644
> --- a/target/riscv/insn_trans/trans_rvh.c.inc
> +++ b/target/riscv/insn_trans/trans_rvh.c.inc
> @@ -20,6 +20,8 @@
> static bool check_access(DisasContext *ctx)
> {
> if (!ctx->hlsx) {
> + tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
> + offsetof(CPURISCVState, bins));
> if (ctx->virt_enabled) {
> generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
> } else {
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
2023-03-30 3:46 [PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault Weiwei Li
2023-03-30 11:13 ` Daniel Henrique Barboza
@ 2023-04-05 3:55 ` Alistair Francis
2023-04-05 6:43 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2023-04-05 3:55 UTC (permalink / raw)
To: Weiwei Li
Cc: qemu-riscv, qemu-devel, palmer, alistair.francis, bin.meng,
dbarboza, zhiwei_liu, wangjunqiang, lazyparser
On Thu, Mar 30, 2023 at 1:47 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> decode_save_opc() will not work for generate_exception(), since 0 is passed
> to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
> not be restored in this case.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvh.c.inc | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
> index 9248b48c36..4b730cd492 100644
> --- a/target/riscv/insn_trans/trans_rvh.c.inc
> +++ b/target/riscv/insn_trans/trans_rvh.c.inc
> @@ -20,6 +20,8 @@
> static bool check_access(DisasContext *ctx)
> {
> if (!ctx->hlsx) {
> + tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
> + offsetof(CPURISCVState, bins));
> if (ctx->virt_enabled) {
> generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
> } else {
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
2023-03-30 3:46 [PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault Weiwei Li
2023-03-30 11:13 ` Daniel Henrique Barboza
2023-04-05 3:55 ` Alistair Francis
@ 2023-04-05 6:43 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2023-04-05 6:43 UTC (permalink / raw)
To: Weiwei Li
Cc: qemu-riscv, qemu-devel, palmer, alistair.francis, bin.meng,
dbarboza, zhiwei_liu, wangjunqiang, lazyparser
On Thu, Mar 30, 2023 at 1:47 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> decode_save_opc() will not work for generate_exception(), since 0 is passed
> to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
> not be restored in this case.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/insn_trans/trans_rvh.c.inc | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
> index 9248b48c36..4b730cd492 100644
> --- a/target/riscv/insn_trans/trans_rvh.c.inc
> +++ b/target/riscv/insn_trans/trans_rvh.c.inc
> @@ -20,6 +20,8 @@
> static bool check_access(DisasContext *ctx)
> {
> if (!ctx->hlsx) {
> + tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
> + offsetof(CPURISCVState, bins));
> if (ctx->virt_enabled) {
> generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
> } else {
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-04-05 6:43 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2023-03-30 3:46 [PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault Weiwei Li
2023-03-30 11:13 ` Daniel Henrique Barboza
2023-04-05 3:55 ` Alistair Francis
2023-04-05 6:43 ` Alistair Francis
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