qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Alistair Francis <alistair23@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Patch Tracking <patches@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 3/7] hw/arm/mps2: Add UARTs
Date: Thu, 13 Jul 2017 09:37:34 +0200	[thread overview]
Message-ID: <CAKmqyKMAuB9KbogvjzZtxWeFcHpb2O1T6dH1v4MrDtbm41CtiQ@mail.gmail.com> (raw)
In-Reply-To: <1499771839-32518-4-git-send-email-peter.maydell@linaro.org>

On Tue, Jul 11, 2017 at 1:17 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> Add the UARTs to the MPS2 board models.
>
> Unfortunately the details of the wiring of the interrupts through
> various OR gates differ between AN511 and AN385 so this can't
> be purely a data-driven difference.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>

Woo! I'm glad the OR IRQ stuff is useful.

Thanks,
Alistair

> ---
>  hw/arm/mps2.c | 86 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 86 insertions(+)
>
> diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
> index 28838bc..1b60b12 100644
> --- a/hw/arm/mps2.c
> +++ b/hw/arm/mps2.c
> @@ -27,9 +27,12 @@
>  #include "qemu/error-report.h"
>  #include "hw/arm/arm.h"
>  #include "hw/arm/armv7m.h"
> +#include "hw/or-irq.h"
>  #include "hw/boards.h"
>  #include "exec/address-spaces.h"
> +#include "sysemu/sysemu.h"
>  #include "hw/misc/unimp.h"
> +#include "hw/char/cmsdk-apb-uart.h"
>
>  typedef enum MPS2FPGAType {
>      FPGA_AN385,
> @@ -208,6 +211,89 @@ static void mps2_common_init(MachineState *machine)
>      create_unimplemented_device("Ethernet", 0x40200000, 0x00100000);
>      create_unimplemented_device("VGA", 0x41000000, 0x0200000);
>
> +    switch (mmc->fpga_type) {
> +    case FPGA_AN385:
> +    {
> +        /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
> +         * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
> +         */
> +        Object *orgate;
> +        DeviceState *orgate_dev;
> +        int i;
> +
> +        orgate = object_new(TYPE_OR_IRQ);
> +        object_property_set_int(orgate, 6, "num-lines", &error_fatal);
> +        object_property_set_bool(orgate, true, "realized", &error_fatal);
> +        orgate_dev = DEVICE(orgate);
> +        qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
> +
> +        for (i = 0; i < 5; i++) {
> +            hwaddr uartbase[] = {0x40004000, 0x40005000, 0x40006000,
> +                                 0x40007000, 0x40009000};
> +            Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL;
> +            /* RX irq number; TX irq is always one greater */
> +            int uartirq[] = {0, 2, 4, 18, 20};
> +            qemu_irq txovrint = NULL, rxovrint = NULL;
> +
> +            if (i < 3) {
> +                txovrint = qdev_get_gpio_in(orgate_dev, i * 2);
> +                rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1);
> +            }
> +
> +            cmsdk_apb_uart_create(uartbase[i],
> +                                  qdev_get_gpio_in(armv7m, uartirq[i] + 1),
> +                                  qdev_get_gpio_in(armv7m, uartirq[i]),
> +                                  txovrint, rxovrint,
> +                                  NULL,
> +                                  uartchr, SYSCLK_FRQ);
> +        }
> +        break;
> +    }
> +    case FPGA_AN511:
> +    {
> +        /* The overflow IRQs for all UARTs are ORed together.
> +         * Tx and Rx IRQs for each UART are ORed together.
> +         */
> +        Object *orgate;
> +        DeviceState *orgate_dev;
> +        int i;
> +
> +        orgate = object_new(TYPE_OR_IRQ);
> +        object_property_set_int(orgate, 10, "num-lines", &error_fatal);
> +        object_property_set_bool(orgate, true, "realized", &error_fatal);
> +        orgate_dev = DEVICE(orgate);
> +        qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
> +
> +        for (i = 0; i < 5; i++) {
> +            /* system irq numbers for the combined tx/rx for each UART */
> +            const int uart_txrx_irqno[] = {0, 2, 45, 46, 56};
> +            hwaddr uartbase[] = {0x40004000, 0x40005000, 0x4002c000,
> +                                 0x4002d000, 0x4002e000};
> +            Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL;
> +            Object *txrx_orgate;
> +            DeviceState *txrx_orgate_dev;
> +
> +            txrx_orgate = object_new(TYPE_OR_IRQ);
> +            object_property_set_int(txrx_orgate, 2, "num-lines", &error_fatal);
> +            object_property_set_bool(txrx_orgate, true, "realized",
> +                                     &error_fatal);
> +            txrx_orgate_dev = DEVICE(txrx_orgate);
> +            qdev_connect_gpio_out(txrx_orgate_dev, 0,
> +                                  qdev_get_gpio_in(armv7m, uart_txrx_irqno[i]));
> +            cmsdk_apb_uart_create(uartbase[i],
> +                                  qdev_get_gpio_in(txrx_orgate_dev, 0),
> +                                  qdev_get_gpio_in(txrx_orgate_dev, 1),
> +                                  qdev_get_gpio_in(orgate_dev, 0),
> +                                  qdev_get_gpio_in(orgate_dev, 1),
> +                                  NULL,
> +                                  uartchr, SYSCLK_FRQ);
> +        }
> +        break;
> +    }
> +    default:
> +        g_assert_not_reached();
> +    }
> +
>      system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
>
>      armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> --
> 2.7.4
>
>

  reply	other threads:[~2017-07-13  7:38 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-11 11:17 [Qemu-devel] [PATCH 0/7] ARM: implement MPS2 board (with 2 FPGA flavours) Peter Maydell
2017-07-11 11:17 ` [Qemu-devel] [PATCH 1/7] hw/arm/mps2: Implement skeleton mps2-an385 and mps2-an511 board models Peter Maydell
2017-07-11 14:33   ` Alistair Francis
2017-07-11 16:35     ` Peter Maydell
2017-07-11 17:47       ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-07-13  7:27       ` [Qemu-devel] " Alistair Francis
2017-07-13 10:39         ` Peter Maydell
2017-07-11 11:17 ` [Qemu-devel] [PATCH 2/7] hw/char/cmsdk-apb-uart.c: Implement CMSDK APB UART Peter Maydell
2017-07-11 15:12   ` Alistair Francis
2017-07-11 15:33     ` Peter Maydell
2017-07-11 15:40       ` Alistair Francis
2017-07-11 16:45         ` Peter Maydell
2017-07-13  7:32           ` Alistair Francis
2017-07-11 17:44     ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-07-11 20:42   ` [Qemu-devel] " Philippe Mathieu-Daudé
2017-07-11 20:51     ` Peter Maydell
2017-07-11 11:17 ` [Qemu-devel] [PATCH 3/7] hw/arm/mps2: Add UARTs Peter Maydell
2017-07-13  7:37   ` Alistair Francis [this message]
2017-07-11 11:17 ` [Qemu-devel] [PATCH 4/7] hw/char/cmsdk-apb-timer: Implement CMSDK APB timer device Peter Maydell
2017-07-14  5:13   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-07-11 11:17 ` [Qemu-devel] [PATCH 5/7] hw/arm/mps2: Add timers Peter Maydell
2017-07-14  5:13   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-07-11 11:17 ` [Qemu-devel] [PATCH 6/7] hw/misc/mps2_scc: Implement MPS2 Serial Communication Controller Peter Maydell
2017-07-11 12:53   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-07-11 13:09     ` Peter Maydell
2017-07-11 11:17 ` [Qemu-devel] [PATCH 7/7] hw/arm/mps2: Add SCC Peter Maydell
2017-07-11 12:55   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-07-11 12:11 ` [Qemu-devel] [PATCH 0/7] ARM: implement MPS2 board (with 2 FPGA flavours) Philippe Mathieu-Daudé
2017-07-11 12:45   ` Peter Maydell
2017-07-11 12:46 ` no-reply
2017-07-11 12:51   ` Peter Maydell
2017-07-11 14:00 ` no-reply
2017-07-11 15:19   ` Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAKmqyKMAuB9KbogvjzZtxWeFcHpb2O1T6dH1v4MrDtbm41CtiQ@mail.gmail.com \
    --to=alistair23@gmail.com \
    --cc=patches@linaro.org \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).