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Thu, 06 Jan 2022 13:24:31 -0800 (PST) MIME-Version: 1.0 References: <20220106210108.138226-1-frederic.petrot@univ-grenoble-alpes.fr> <20220106210108.138226-8-frederic.petrot@univ-grenoble-alpes.fr> In-Reply-To: <20220106210108.138226-8-frederic.petrot@univ-grenoble-alpes.fr> From: Alistair Francis Date: Fri, 7 Jan 2022 07:24:05 +1000 Message-ID: Subject: Re: [PATCH v8 07/18] target/riscv: setup everything for rv64 to support rv128 execution To: =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::136 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::136; envelope-from=alistair23@gmail.com; helo=mail-il1-x136.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Bin Meng , Richard Henderson , "qemu-devel@nongnu.org Developers" , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Palmer Dabbelt , Fabien Portas , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, Jan 7, 2022 at 7:04 AM Fr=C3=A9d=C3=A9ric P=C3=A9trot wrote: > > This patch adds the support of the '-cpu rv128' option to > qemu-system-riscv64 so that we can indicate that we want to run rv128 > executables. > Still, there is no support for 128-bit insns at that stage so qemu fails > miserably (as expected) if launched with this option. > > Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot > Co-authored-by: Fabien Portas > Reviewed-by: Alistair Francis > --- > include/disas/dis-asm.h | 1 + > target/riscv/cpu.h | 1 + > disas/riscv.c | 5 +++++ > target/riscv/cpu.c | 20 ++++++++++++++++++++ > target/riscv/gdbstub.c | 5 +++++ > 5 files changed, 32 insertions(+) > > diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h > index 08e1beec85..102a1e7f50 100644 > --- a/include/disas/dis-asm.h > +++ b/include/disas/dis-asm.h > @@ -459,6 +459,7 @@ int print_insn_nios2(bfd_vma, disassemble_info*); > int print_insn_xtensa (bfd_vma, disassemble_info*); > int print_insn_riscv32 (bfd_vma, disassemble_info*); > int print_insn_riscv64 (bfd_vma, disassemble_info*); > +int print_insn_riscv128 (bfd_vma, disassemble_info*); > int print_insn_rx(bfd_vma, disassemble_info *); > int print_insn_hexagon(bfd_vma, disassemble_info *); > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index fa5d238530..efe481f5fb 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -38,6 +38,7 @@ > #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") > #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") > #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") > +#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("rv128") As this series only adds partial support for 128-bit support, I think we should probably change this to "x-rv128". That way we indicate to users that it is experimental. That allows us more flexibility in the future to have breaking changes and will hopefully avoid confusion about the current state. What do you think? I can just make the change when I apply the patches. Alistair