From: Alistair Francis <alistair23@gmail.com>
To: Frank Chang <frank.chang@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: Re: [PATCH 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
Date: Tue, 18 Jan 2022 08:55:43 +1000 [thread overview]
Message-ID: <CAKmqyKMCDArArm4jTmcOMtCEL8+z_u4UL6rGJqVO4dwT1RRUCg@mail.gmail.com> (raw)
In-Reply-To: <20211229023348.12606-14-frank.chang@sifive.com>
On Wed, Dec 29, 2021 at 12:48 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Zve32f extension requires the scalar processor to implement the F
> extension and implement all vector floating-point instructions for
> floating-point operands with EEW=32 (i.e., no widening floating-point
> operations).
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index c6280c7b0b..1f5a75eca7 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -66,6 +66,17 @@ static bool require_scale_rvf(DisasContext *s)
> }
> }
>
> +static bool require_zve32f(DisasContext *s)
> +{
> + /* RVV + Zve32f = RVV. */
> + if (has_ext(s, RVV)) {
> + return true;
> + }
> +
> + /* Zve32f doesn't support FP64. (Section 18.2) */
> + return s->ext_zve32f ? s->sew <= MO_32 : true;
> +}
> +
> static bool require_zve64f(DisasContext *s)
> {
> /* RVV + Zve64f = RVV. */
> @@ -2227,6 +2238,7 @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
> + require_zve32f(s) &&
> require_zve64f(s);
> }
>
> @@ -2308,6 +2320,7 @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> vext_check_ss(s, a->rd, a->rs2, a->vm) &&
> + require_zve32f(s) &&
> require_zve64f(s);
> }
>
> @@ -2530,6 +2543,7 @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
> vext_check_isa_ill(s) &&
> /* OPFV instructions ignore vs1 check */
> vext_check_ss(s, a->rd, a->rs2, a->vm) &&
> + require_zve32f(s) &&
> require_zve64f(s);
> }
>
> @@ -2596,6 +2610,7 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
> + require_zve32f(s) &&
> require_zve64f(s);
> }
>
> @@ -2610,6 +2625,7 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> vext_check_ms(s, a->rd, a->rs2) &&
> + require_zve32f(s) &&
> require_zve64f(s);
> }
>
> @@ -2632,6 +2648,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> require_align(a->rd, s->lmul) &&
> + require_zve32f(s) &&
> require_zve64f(s)) {
> gen_set_rm(s, RISCV_FRM_DYN);
>
> @@ -3366,6 +3383,7 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
> if (require_rvv(s) &&
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> + require_zve32f(s) &&
> require_zve64f(s)) {
> gen_set_rm(s, RISCV_FRM_DYN);
>
> @@ -3393,6 +3411,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
> if (require_rvv(s) &&
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> + require_zve32f(s) &&
> require_zve64f(s)) {
> gen_set_rm(s, RISCV_FRM_DYN);
>
> @@ -3445,6 +3464,7 @@ static bool fslideup_check(DisasContext *s, arg_rmrr *a)
> {
> return slideup_check(s, a) &&
> require_rvf(s) &&
> + require_zve32f(s) &&
> require_zve64f(s);
> }
>
> @@ -3452,6 +3472,7 @@ static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
> {
> return slidedown_check(s, a) &&
> require_rvf(s) &&
> + require_zve32f(s) &&
> require_zve64f(s);
> }
>
> --
> 2.31.1
>
>
next prev parent reply other threads:[~2022-01-17 22:58 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-29 2:33 [PATCH 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
2021-12-29 2:33 ` [PATCH 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V frank.chang
2022-01-17 22:23 ` Alistair Francis
2021-12-29 2:33 ` [PATCH 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns frank.chang
2022-01-17 22:21 ` Alistair Francis
2021-12-29 2:33 ` [PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns frank.chang
2022-01-17 22:27 ` Alistair Francis
2022-01-18 1:37 ` Frank Chang
2021-12-29 2:33 ` [PATCH 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns frank.chang
2022-01-17 22:30 ` Alistair Francis
2021-12-29 2:33 ` [PATCH 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns frank.chang
2022-01-17 22:31 ` Alistair Francis
2021-12-29 2:33 ` [PATCH 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns frank.chang
2022-01-17 22:39 ` Alistair Francis
2021-12-29 2:33 ` [PATCH 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns frank.chang
2022-01-17 22:50 ` Alistair Francis
2021-12-29 2:33 ` [PATCH 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns frank.chang
2022-01-17 22:51 ` Alistair Francis
2021-12-29 2:33 ` [PATCH 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing " frank.chang
2022-01-17 22:53 ` Alistair Francis
2021-12-29 2:33 ` [PATCH 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on frank.chang
2022-01-17 22:53 ` Alistair Francis
2021-12-29 2:33 ` [PATCH 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V frank.chang
2022-01-17 22:54 ` Alistair Francis
2021-12-29 2:33 ` [PATCH 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns frank.chang
2022-01-17 22:54 ` Alistair Francis
2021-12-29 2:33 ` [PATCH 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns frank.chang
2022-01-17 22:55 ` Alistair Francis [this message]
2021-12-29 2:33 ` [PATCH 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns frank.chang
2022-01-17 22:56 ` Alistair Francis
2021-12-29 2:33 ` [PATCH 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns frank.chang
2022-01-17 22:56 ` Alistair Francis
2021-12-29 2:33 ` [PATCH 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing " frank.chang
2022-01-17 22:57 ` Alistair Francis
2021-12-29 2:33 ` [PATCH 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on frank.chang
2022-01-17 22:57 ` Alistair Francis
2022-01-17 12:55 ` [PATCH 00/17] Add RISC-V RVV Zve32f and Zve64f extensions Frank Chang
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