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Mon, 09 Jan 2023 14:54:35 -0800 (PST) MIME-Version: 1.0 References: <20221228062028.29415-1-liweiwei@iscas.ac.cn> In-Reply-To: <20221228062028.29415-1-liweiwei@iscas.ac.cn> From: Alistair Francis Date: Tue, 10 Jan 2023 08:54:09 +1000 Message-ID: Subject: Re: [PATCH v9 0/9] support subsets of code size reduction extension To: Weiwei Li Cc: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wangjunqiang@iscas.ac.cn, lazyparser@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a2f; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Dec 28, 2022 at 4:23 PM Weiwei Li wrote: > > This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version instru= ctions. > > Specification: > https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specifica= tion > > The port is available here: > https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v9 > > To test Zc* implementation, specify cpu argument with 'x-zca=3Dtrue,x-zcb= =3Dtrue,x-zcf=3Dtrue,f=3Dtrue" and "x-zcd=3Dtrue,d=3Dtrue" (or "x-zcmp=3Dtr= ue,x-zcmt=3Dtrue" with c or d=3Dfalse) to enable Zca/Zcb/Zcf and Zcd(or Zcm= p,Zcmt) extensions support. > > > This implementation can pass the basic zc tests from https://github.com/y= ulong-plct/zc-test > > v9: > * rebase on riscv-to-apply.next > > v8: > * improve disas support in Patch 9 > > v7: > * Fix description for Zca > > v6=EF=BC=9A > * fix base address for jump table in Patch 7 > * rebase on riscv-to-apply.next > > v5: > * fix exception unwind problem for cpu_ld*_code in helper of cm_jalt > > v4: > * improve Zcmp suggested by Richard > * fix stateen related check for Zcmt > > v3: > * update the solution for Zcf to the way of Zcd > * update Zcb to reuse gen_load/store > * use trans function instead of helper for push/pop > > v2: > * add check for relationship between Zca/Zcf/Zcd with C/F/D based on rela= ted discussion in review of Zc* spec > * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/= zcmt > > Weiwei Li (9): > target/riscv: add cfg properties for Zc* extension > target/riscv: add support for Zca extension > target/riscv: add support for Zcf extension > target/riscv: add support for Zcd extension > target/riscv: add support for Zcb extension > target/riscv: add support for Zcmp extension > target/riscv: add support for Zcmt extension > target/riscv: expose properties for Zc* extension > disas/riscv.c: add disasm support for Zc* Thanks! Applied to riscv-to-apply.next Alistair > > disas/riscv.c | 228 +++++++++++++++- > target/riscv/cpu.c | 56 ++++ > target/riscv/cpu.h | 10 + > target/riscv/cpu_bits.h | 7 + > target/riscv/csr.c | 38 ++- > target/riscv/helper.h | 3 + > target/riscv/insn16.decode | 63 ++++- > target/riscv/insn_trans/trans_rvd.c.inc | 18 ++ > target/riscv/insn_trans/trans_rvf.c.inc | 18 ++ > target/riscv/insn_trans/trans_rvi.c.inc | 4 +- > target/riscv/insn_trans/trans_rvzce.c.inc | 313 ++++++++++++++++++++++ > target/riscv/machine.c | 19 ++ > target/riscv/meson.build | 3 +- > target/riscv/translate.c | 15 +- > target/riscv/zce_helper.c | 55 ++++ > 15 files changed, 834 insertions(+), 16 deletions(-) > create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc > create mode 100644 target/riscv/zce_helper.c > > -- > 2.25.1 > >