* [PATCH 0/3] Trapped instruction encoding support
@ 2020-07-29 11:27 Anup Patel
2020-07-29 11:27 ` [PATCH 1/3] target/riscv: Optional feature to provide trapped instruction in CSRs Anup Patel
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Anup Patel @ 2020-07-29 11:27 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel
With RISC-V H-extension support, a RISC-V implementation can provide trapped
instruction encoding for almost all traps/exceptions.
For illegal/virtual instruction traps, the instruction encoding is available
in STVAL/MTVAL CSR.
For load/store faults, a transformed encoding of the trapped instruction is
available in MTINST/HTINST CSR.
This series implements optional RISC-V HART feature to provide trapped
instruction encoding in appropriate CSR.
These patches can be found in riscv_trap_insn_v1, branch at:
https://github.com/avpatel/qemu.git
Anup Patel (3):
target/riscv: Optional feature to provide trapped instruction in CSRs
target/riscv: Fix write_htinst() implementation
target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt()
target/riscv/cpu.c | 7 ++
target/riscv/cpu.h | 11 ++-
target/riscv/cpu_helper.c | 172 +++++++++++++++++++++++++++++++++++++-
target/riscv/csr.c | 1 +
target/riscv/instmap.h | 41 +++++++++
target/riscv/translate.c | 14 +++-
6 files changed, 241 insertions(+), 5 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 1/3] target/riscv: Optional feature to provide trapped instruction in CSRs 2020-07-29 11:27 [PATCH 0/3] Trapped instruction encoding support Anup Patel @ 2020-07-29 11:27 ` Anup Patel 2020-08-12 22:37 ` Alistair Francis 2020-07-29 11:28 ` [PATCH 2/3] target/riscv: Fix write_htinst() implementation Anup Patel 2020-07-29 11:28 ` [PATCH 3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt() Anup Patel 2 siblings, 1 reply; 8+ messages in thread From: Anup Patel @ 2020-07-29 11:27 UTC (permalink / raw) To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel The RISC-V spec allows implementations to provide trapped instruction opcode in MTVAL/STVAL CSR for illegal/virtual instruction traps. This is totally optional and most RISC-V implementations always set zero in the MTVAL/STVAL CSR for illegal/virtual instruction traps. When trapped instruction opcode is available in MTVAL/STVAL CSR, the M-mode runtime firmware (and Hypervisors) can skip unprivlege access for reading trapped instruction opcode which in-turn will speed-up the illegal/virtual instruction trap handling. This patch implements RISCV_FEATURE_TINST feature which when enabled provides original trapped instruction opcode in MTVAL/STVAL CSRs for illegal/virtual instruction trap. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- target/riscv/cpu.c | 7 +++++++ target/riscv/cpu.h | 11 ++++++++++- target/riscv/cpu_helper.c | 6 ++++++ target/riscv/translate.c | 14 +++++++++++++- 4 files changed, 36 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eeb91f8513..ec098e445e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -317,6 +317,7 @@ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, target_ulong *data) { env->pc = data[0]; + env->trap_insn = data[1]; } static void riscv_cpu_reset(DeviceState *dev) @@ -332,6 +333,7 @@ static void riscv_cpu_reset(DeviceState *dev) env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); env->mcause = 0; env->pc = env->resetvec; + env->trap_insn = 0; #endif cs->exception_index = EXCP_NONE; env->load_res = -1; @@ -387,6 +389,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_feature(env, RISCV_FEATURE_PMP); } + if (cpu->cfg.tinst) { + set_feature(env, RISCV_FEATURE_TINST); + } + /* If misa isn't set (rv32 and rv64 machines) set it here */ if (!env->misa) { /* Do some ISA extension error checking */ @@ -487,6 +493,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_BOOL("tinst", RISCVCPU, cfg.tinst, false), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1bb5271511..33984539d7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -26,6 +26,12 @@ #define TCG_GUEST_DEFAULT_MO 0 +/* + * RISC-V-specific extra insn start words: + * 1: Original instruction opcode + */ +#define TARGET_INSN_START_EXTRA_WORDS 1 + #define TYPE_RISCV_CPU "riscv-cpu" #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU @@ -70,7 +76,8 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, - RISCV_FEATURE_MISA + RISCV_FEATURE_MISA, + RISCV_FEATURE_TINST }; #define PRIV_VERSION_1_10_0 0x00011000 @@ -97,6 +104,7 @@ struct CPURISCVState { target_ulong frm; target_ulong badaddr; + target_ulong trap_insn; target_ulong guest_phys_fault_addr; target_ulong priv_ver; @@ -264,6 +272,7 @@ typedef struct RISCVCPU { char *user_spec; bool mmu; bool pmp; + bool tinst; } cfg; } RISCVCPU; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index eccd80cfef..e4bd45d66a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -864,6 +864,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_STORE_PAGE_FAULT: tval = env->badaddr; break; + case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: + case RISCV_EXCP_ILLEGAL_INST: + if (riscv_feature(env, RISCV_FEATURE_TINST)) { + tval = env->trap_insn; + } + break; default: break; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1d973b62e9..03954bff62 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -56,6 +56,8 @@ typedef struct DisasContext { to reset this known value. */ int frm; bool ext_ifencei; + /* TCG op of the current insn_start. */ + TCGOp *insn_start; } DisasContext; #ifdef TARGET_RISCV64 @@ -717,6 +719,13 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, /* Include the auto-generated decoder for 16 bit insn */ #include "decode_insn16.inc.c" +static inline void decode_save_opc(DisasContext *ctx, target_ulong opc) +{ + assert(ctx->insn_start != NULL); + tcg_set_insn_start_param(ctx->insn_start, 1, opc); + ctx->insn_start = NULL; +} + static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) { /* check for compressed insn */ @@ -724,6 +733,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) if (!has_ext(ctx, RVC)) { gen_exception_illegal(ctx); } else { + decode_save_opc(ctx, opcode); ctx->pc_succ_insn = ctx->base.pc_next + 2; if (!decode_insn16(ctx, opcode)) { /* fall back to old decoder */ @@ -734,6 +744,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) uint32_t opcode32 = opcode; opcode32 = deposit32(opcode32, 16, 16, translator_lduw(env, ctx->base.pc_next + 2)); + decode_save_opc(ctx, opcode32); ctx->pc_succ_insn = ctx->base.pc_next + 4; if (!decode_insn32(ctx, opcode32)) { gen_exception_illegal(ctx); @@ -773,7 +784,8 @@ static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0); + ctx->insn_start = tcg_last_op(); } static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] target/riscv: Optional feature to provide trapped instruction in CSRs 2020-07-29 11:27 ` [PATCH 1/3] target/riscv: Optional feature to provide trapped instruction in CSRs Anup Patel @ 2020-08-12 22:37 ` Alistair Francis 0 siblings, 0 replies; 8+ messages in thread From: Alistair Francis @ 2020-08-12 22:37 UTC (permalink / raw) To: Anup Patel Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel, qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis, Palmer Dabbelt On Wed, Jul 29, 2020 at 4:29 AM Anup Patel <anup.patel@wdc.com> wrote: > > The RISC-V spec allows implementations to provide trapped instruction > opcode in MTVAL/STVAL CSR for illegal/virtual instruction traps. This > is totally optional and most RISC-V implementations always set zero > in the MTVAL/STVAL CSR for illegal/virtual instruction traps. > > When trapped instruction opcode is available in MTVAL/STVAL CSR, the > M-mode runtime firmware (and Hypervisors) can skip unprivlege access > for reading trapped instruction opcode which in-turn will speed-up > the illegal/virtual instruction trap handling. > > This patch implements RISCV_FEATURE_TINST feature which when enabled > provides original trapped instruction opcode in MTVAL/STVAL CSRs for > illegal/virtual instruction trap. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 7 +++++++ > target/riscv/cpu.h | 11 ++++++++++- > target/riscv/cpu_helper.c | 6 ++++++ > target/riscv/translate.c | 14 +++++++++++++- > 4 files changed, 36 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index eeb91f8513..ec098e445e 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -317,6 +317,7 @@ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, > target_ulong *data) > { > env->pc = data[0]; > + env->trap_insn = data[1]; > } > > static void riscv_cpu_reset(DeviceState *dev) > @@ -332,6 +333,7 @@ static void riscv_cpu_reset(DeviceState *dev) > env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); > env->mcause = 0; > env->pc = env->resetvec; > + env->trap_insn = 0; > #endif > cs->exception_index = EXCP_NONE; > env->load_res = -1; > @@ -387,6 +389,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > set_feature(env, RISCV_FEATURE_PMP); > } > > + if (cpu->cfg.tinst) { > + set_feature(env, RISCV_FEATURE_TINST); > + } > + > /* If misa isn't set (rv32 and rv64 machines) set it here */ > if (!env->misa) { > /* Do some ISA extension error checking */ > @@ -487,6 +493,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > + DEFINE_PROP_BOOL("tinst", RISCVCPU, cfg.tinst, false), > DEFINE_PROP_END_OF_LIST(), > }; > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 1bb5271511..33984539d7 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -26,6 +26,12 @@ > > #define TCG_GUEST_DEFAULT_MO 0 > > +/* > + * RISC-V-specific extra insn start words: > + * 1: Original instruction opcode > + */ > +#define TARGET_INSN_START_EXTRA_WORDS 1 > + > #define TYPE_RISCV_CPU "riscv-cpu" > > #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU > @@ -70,7 +76,8 @@ > enum { > RISCV_FEATURE_MMU, > RISCV_FEATURE_PMP, > - RISCV_FEATURE_MISA > + RISCV_FEATURE_MISA, > + RISCV_FEATURE_TINST > }; > > #define PRIV_VERSION_1_10_0 0x00011000 > @@ -97,6 +104,7 @@ struct CPURISCVState { > target_ulong frm; > > target_ulong badaddr; > + target_ulong trap_insn; > target_ulong guest_phys_fault_addr; > > target_ulong priv_ver; > @@ -264,6 +272,7 @@ typedef struct RISCVCPU { > char *user_spec; > bool mmu; > bool pmp; > + bool tinst; > } cfg; > } RISCVCPU; > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index eccd80cfef..e4bd45d66a 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -864,6 +864,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) > case RISCV_EXCP_STORE_PAGE_FAULT: > tval = env->badaddr; > break; > + case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: > + case RISCV_EXCP_ILLEGAL_INST: > + if (riscv_feature(env, RISCV_FEATURE_TINST)) { > + tval = env->trap_insn; > + } > + break; > default: > break; > } > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 1d973b62e9..03954bff62 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -56,6 +56,8 @@ typedef struct DisasContext { > to reset this known value. */ > int frm; > bool ext_ifencei; > + /* TCG op of the current insn_start. */ > + TCGOp *insn_start; > } DisasContext; > > #ifdef TARGET_RISCV64 > @@ -717,6 +719,13 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, > /* Include the auto-generated decoder for 16 bit insn */ > #include "decode_insn16.inc.c" > > +static inline void decode_save_opc(DisasContext *ctx, target_ulong opc) > +{ > + assert(ctx->insn_start != NULL); > + tcg_set_insn_start_param(ctx->insn_start, 1, opc); > + ctx->insn_start = NULL; > +} > + > static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) > { > /* check for compressed insn */ > @@ -724,6 +733,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) > if (!has_ext(ctx, RVC)) { > gen_exception_illegal(ctx); > } else { > + decode_save_opc(ctx, opcode); > ctx->pc_succ_insn = ctx->base.pc_next + 2; > if (!decode_insn16(ctx, opcode)) { > /* fall back to old decoder */ > @@ -734,6 +744,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) > uint32_t opcode32 = opcode; > opcode32 = deposit32(opcode32, 16, 16, > translator_lduw(env, ctx->base.pc_next + 2)); > + decode_save_opc(ctx, opcode32); > ctx->pc_succ_insn = ctx->base.pc_next + 4; > if (!decode_insn32(ctx, opcode32)) { > gen_exception_illegal(ctx); > @@ -773,7 +784,8 @@ static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) > { > DisasContext *ctx = container_of(dcbase, DisasContext, base); > > - tcg_gen_insn_start(ctx->base.pc_next); > + tcg_gen_insn_start(ctx->base.pc_next, 0); > + ctx->insn_start = tcg_last_op(); > } > > static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, > -- > 2.25.1 > > ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/3] target/riscv: Fix write_htinst() implementation 2020-07-29 11:27 [PATCH 0/3] Trapped instruction encoding support Anup Patel 2020-07-29 11:27 ` [PATCH 1/3] target/riscv: Optional feature to provide trapped instruction in CSRs Anup Patel @ 2020-07-29 11:28 ` Anup Patel 2020-08-10 22:37 ` Alistair Francis 2020-07-29 11:28 ` [PATCH 3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt() Anup Patel 2 siblings, 1 reply; 8+ messages in thread From: Anup Patel @ 2020-07-29 11:28 UTC (permalink / raw) To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel The htinst CSR is writeable from M-mode and HS-mode so we should not ignore writes to htinst CSR. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- target/riscv/csr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f985b85de4..99fcb7f67d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -943,6 +943,7 @@ static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val) static int write_htinst(CPURISCVState *env, int csrno, target_ulong val) { + env->htinst = val; return 0; } -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] target/riscv: Fix write_htinst() implementation 2020-07-29 11:28 ` [PATCH 2/3] target/riscv: Fix write_htinst() implementation Anup Patel @ 2020-08-10 22:37 ` Alistair Francis 0 siblings, 0 replies; 8+ messages in thread From: Alistair Francis @ 2020-08-10 22:37 UTC (permalink / raw) To: Anup Patel Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel, qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis, Palmer Dabbelt On Wed, Jul 29, 2020 at 4:30 AM Anup Patel <anup.patel@wdc.com> wrote: > > The htinst CSR is writeable from M-mode and HS-mode so > we should not ignore writes to htinst CSR. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/csr.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index f985b85de4..99fcb7f67d 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -943,6 +943,7 @@ static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val) > > static int write_htinst(CPURISCVState *env, int csrno, target_ulong val) > { > + env->htinst = val; > return 0; > } > > -- > 2.25.1 > > ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt() 2020-07-29 11:27 [PATCH 0/3] Trapped instruction encoding support Anup Patel 2020-07-29 11:27 ` [PATCH 1/3] target/riscv: Optional feature to provide trapped instruction in CSRs Anup Patel 2020-07-29 11:28 ` [PATCH 2/3] target/riscv: Fix write_htinst() implementation Anup Patel @ 2020-07-29 11:28 ` Anup Patel 2020-08-12 23:16 ` Alistair Francis 2 siblings, 1 reply; 8+ messages in thread From: Anup Patel @ 2020-07-29 11:28 UTC (permalink / raw) To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel When RISCV_FEATURE_TINST feature is enabled, we should write transformed instruction encoding of the trapped instruction in MTINST/HTINST CSR at time of taking trap. We update riscv_cpu_do_interrupt() as-per above. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- target/riscv/cpu_helper.c | 166 +++++++++++++++++++++++++++++++++++++- target/riscv/instmap.h | 41 ++++++++++ 2 files changed, 204 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e4bd45d66a..97ae23ad2b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -22,6 +22,7 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "exec/exec-all.h" +#include "instmap.h" #include "tcg/tcg-op.h" #include "trace.h" @@ -820,6 +821,151 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, #endif } +static target_ulong riscv_transformed_insn(CPURISCVState *env, + int xlen, target_ulong insn) +{ + target_ulong xinsn = 0; + + if ((insn & 0x3) != 0x3) { + /* Transform 16bit instruction into 32bit instruction */ + switch (GET_C_OP(insn)) { + case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLD_LQ: + if (xlen != 128) { /* C.FLD (RV32/64) */ + xinsn = OPC_RISC_FLD; + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_I_IMM(xinsn, GET_C_LD_IMM(insn)); + } + break; + case OPC_RISC_C_FUNC_LW: /* C.LW */ + xinsn = OPC_RISC_LW; + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_I_IMM(xinsn, GET_C_LW_IMM(insn)); + break; + case OPC_RISC_C_FUNC_FLW_LD: + if (xlen == 32) { /* C.FLW (RV32) */ + xinsn = OPC_RISC_FLW; + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_I_IMM(xinsn, GET_C_LW_IMM(insn)); + } else { /* C.LD (RV64/RV128) */ + xinsn = OPC_RISC_LD; + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_I_IMM(xinsn, GET_C_LD_IMM(insn)); + } + break; + case OPC_RISC_C_FUNC_FSD_SQ: + if (xlen != 128) { /* C.FSD (RV32/64) */ + xinsn = OPC_RISC_FSD; + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_S_IMM(xinsn, GET_C_SD_IMM(insn)); + } + break; + case OPC_RISC_C_FUNC_SW: /* C.SW */ + xinsn = OPC_RISC_SW; + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_S_IMM(xinsn, GET_C_SW_IMM(insn)); + break; + case OPC_RISC_C_FUNC_FSW_SD: + if (xlen == 32) { /* C.FSW (RV32) */ + xinsn = OPC_RISC_FSW; + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_S_IMM(xinsn, GET_C_SW_IMM(insn)); + } else { /* C.SD (RV64/RV128) */ + xinsn = OPC_RISC_SD; + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn = SET_S_IMM(xinsn, GET_C_SD_IMM(insn)); + } + break; + default: + break; + } + break; + case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLDSP_LQSP: + if (xlen != 128) { /* C.FLDSP (RV32/64) */ + xinsn = OPC_RISC_FLD; + xinsn = SET_RD(xinsn, GET_C_RD(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_I_IMM(xinsn, GET_C_LDSP_IMM(insn)); + } + break; + case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ + xinsn = OPC_RISC_LW; + xinsn = SET_RD(xinsn, GET_C_RD(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_I_IMM(xinsn, GET_C_LWSP_IMM(insn)); + break; + case OPC_RISC_C_FUNC_FLWSP_LDSP: + if (xlen == 32) { /* C.FLWSP (RV32) */ + xinsn = OPC_RISC_FLW; + xinsn = SET_RD(xinsn, GET_C_RD(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_I_IMM(xinsn, GET_C_LWSP_IMM(insn)); + } else { /* C.LDSP (RV64/RV128) */ + xinsn = OPC_RISC_LD; + xinsn = SET_RD(xinsn, GET_C_RD(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_I_IMM(xinsn, GET_C_LDSP_IMM(insn)); + } + break; + case OPC_RISC_C_FUNC_FSDSP_SQSP: + if (xlen != 128) { /* C.FSDSP (RV32/64) */ + xinsn = OPC_RISC_FSD; + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_S_IMM(xinsn, GET_C_SDSP_IMM(insn)); + } + break; + case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ + xinsn = OPC_RISC_SW; + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_S_IMM(xinsn, GET_C_SWSP_IMM(insn)); + break; + case 7: + if (xlen == 32) { /* C.FSWSP (RV32) */ + xinsn = OPC_RISC_FSW; + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_S_IMM(xinsn, GET_C_SWSP_IMM(insn)); + } else { /* C.SDSP (RV64/RV128) */ + xinsn = OPC_RISC_SD; + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn = SET_RS1(xinsn, 2); + xinsn = SET_S_IMM(xinsn, GET_C_SDSP_IMM(insn)); + } + break; + default: + break; + } + break; + default: + break; + } + + /* + * Clear Bit1 of transformed instruction to indicate that + * original insruction was a 16bit instruction + */ + xinsn &= ~((target_ulong)0x2); + } else { + /* No need to transform 32bit (or wider) instructions */ + xinsn = insn; + } + + return xinsn; +} + /* * Handle Traps * @@ -842,6 +988,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; target_ulong deleg = async ? env->mideleg : env->medeleg; target_ulong tval = 0; + target_ulong tinst = 0; target_ulong htval = 0; target_ulong mtval2 = 0; @@ -849,20 +996,31 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* set tval to badaddr for traps with address information */ switch (cause) { case RISCV_EXCP_INST_GUEST_PAGE_FAULT: - case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: - case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: force_hs_execp = true; /* fallthrough */ case RISCV_EXCP_INST_ADDR_MIS: case RISCV_EXCP_INST_ACCESS_FAULT: + case RISCV_EXCP_INST_PAGE_FAULT: + tval = env->badaddr; + break; + case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: + case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: + force_hs_execp = true; + /* fallthrough */ case RISCV_EXCP_LOAD_ADDR_MIS: case RISCV_EXCP_STORE_AMO_ADDR_MIS: case RISCV_EXCP_LOAD_ACCESS_FAULT: case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: - case RISCV_EXCP_INST_PAGE_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT: tval = env->badaddr; + if (riscv_feature(env, RISCV_FEATURE_TINST)) { +#if defined(TARGET_RISCV32) + tinst = riscv_transformed_insn(env, 32, env->trap_insn); +#elif defined(TARGET_RISCV64) + tinst = riscv_transformed_insn(env, 64, env->trap_insn); +#endif + } break; case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: case RISCV_EXCP_ILLEGAL_INST: @@ -955,6 +1113,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->sepc = env->pc; env->sbadaddr = tval; env->htval = htval; + env->htinst = tinst; env->pc = (env->stvec >> 2 << 2) + ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_S); @@ -994,6 +1153,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mepc = env->pc; env->mbadaddr = tval; env->mtval2 = mtval2; + env->mtinst = tinst; env->pc = (env->mtvec >> 2 << 2) + ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_M); diff --git a/target/riscv/instmap.h b/target/riscv/instmap.h index 40b6d2b64d..f4ee686c78 100644 --- a/target/riscv/instmap.h +++ b/target/riscv/instmap.h @@ -316,6 +316,12 @@ enum { #define GET_RS2(inst) extract32(inst, 20, 5) #define GET_RD(inst) extract32(inst, 7, 5) #define GET_IMM(inst) sextract64(inst, 20, 12) +#define SET_RS1(inst, val) deposit32(inst, 15, 5, val) +#define SET_RS2(inst, val) deposit32(inst, 20, 5, val) +#define SET_RD(inst, val) deposit32(inst, 7, 5, val) +#define SET_I_IMM(inst, val) deposit32(inst, 20, 12, val) +#define SET_S_IMM(inst, val) \ + deposit32(deposit32(inst, 7, 5, val), 25, 7, (val) >> 5) /* RVC decoding macros */ #define GET_C_IMM(inst) (extract32(inst, 2, 5) \ @@ -346,6 +352,8 @@ enum { | (extract32(inst, 5, 1) << 6)) #define GET_C_LD_IMM(inst) ((extract16(inst, 10, 3) << 3) \ | (extract16(inst, 5, 2) << 6)) +#define GET_C_SW_IMM(inst) GET_C_LW_IMM(inst) +#define GET_C_SD_IMM(inst) GET_C_LD_IMM(inst) #define GET_C_J_IMM(inst) ((extract32(inst, 3, 3) << 1) \ | (extract32(inst, 11, 1) << 4) \ | (extract32(inst, 2, 1) << 5) \ @@ -366,4 +374,37 @@ enum { #define GET_C_RS1S(inst) (8 + extract16(inst, 7, 3)) #define GET_C_RS2S(inst) (8 + extract16(inst, 2, 3)) +#define GET_C_FUNC(inst) extract32(inst, 13, 3) +#define GET_C_OP(inst) extract32(inst, 0, 2) + +enum { + /* RVC Quadrants */ + OPC_RISC_C_OP_QUAD0 = 0x0, + OPC_RISC_C_OP_QUAD1 = 0x1, + OPC_RISC_C_OP_QUAD2 = 0x2 +}; + +enum { + /* RVC Quadrant 0 */ + OPC_RISC_C_FUNC_ADDI4SPN = 0x0, + OPC_RISC_C_FUNC_FLD_LQ = 0x1, + OPC_RISC_C_FUNC_LW = 0x2, + OPC_RISC_C_FUNC_FLW_LD = 0x3, + OPC_RISC_C_FUNC_FSD_SQ = 0x5, + OPC_RISC_C_FUNC_SW = 0x6, + OPC_RISC_C_FUNC_FSW_SD = 0x7 +}; + +enum { + /* RVC Quadrant 2 */ + OPC_RISC_C_FUNC_SLLI_SLLI64 = 0x0, + OPC_RISC_C_FUNC_FLDSP_LQSP = 0x1, + OPC_RISC_C_FUNC_LWSP = 0x2, + OPC_RISC_C_FUNC_FLWSP_LDSP = 0x3, + OPC_RISC_C_FUNC_JR_MV_EBREAK_JALR_ADD = 0x4, + OPC_RISC_C_FUNC_FSDSP_SQSP = 0x5, + OPC_RISC_C_FUNC_SWSP = 0x6, + OPC_RISC_C_FUNC_FSWSP_SDSP = 0x7 +}; + #endif -- 2.25.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt() 2020-07-29 11:28 ` [PATCH 3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt() Anup Patel @ 2020-08-12 23:16 ` Alistair Francis 2020-08-13 15:52 ` Richard Henderson 0 siblings, 1 reply; 8+ messages in thread From: Alistair Francis @ 2020-08-12 23:16 UTC (permalink / raw) To: Anup Patel Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel, qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis, Palmer Dabbelt On Wed, Jul 29, 2020 at 4:32 AM Anup Patel <anup.patel@wdc.com> wrote: > > When RISCV_FEATURE_TINST feature is enabled, we should write > transformed instruction encoding of the trapped instruction > in MTINST/HTINST CSR at time of taking trap. > > We update riscv_cpu_do_interrupt() as-per above. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > --- > target/riscv/cpu_helper.c | 166 +++++++++++++++++++++++++++++++++++++- > target/riscv/instmap.h | 41 ++++++++++ > 2 files changed, 204 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index e4bd45d66a..97ae23ad2b 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -22,6 +22,7 @@ > #include "qemu/main-loop.h" > #include "cpu.h" > #include "exec/exec-all.h" > +#include "instmap.h" > #include "tcg/tcg-op.h" > #include "trace.h" > > @@ -820,6 +821,151 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > #endif > } > > +static target_ulong riscv_transformed_insn(CPURISCVState *env, > + int xlen, target_ulong insn) > +{ > + target_ulong xinsn = 0; > + > + if ((insn & 0x3) != 0x3) { > + /* Transform 16bit instruction into 32bit instruction */ > + switch (GET_C_OP(insn)) { > + case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ > + switch (GET_C_FUNC(insn)) { > + case OPC_RISC_C_FUNC_FLD_LQ: > + if (xlen != 128) { /* C.FLD (RV32/64) */ > + xinsn = OPC_RISC_FLD; > + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); > + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); > + xinsn = SET_I_IMM(xinsn, GET_C_LD_IMM(insn)); > + } > + break; > + case OPC_RISC_C_FUNC_LW: /* C.LW */ > + xinsn = OPC_RISC_LW; > + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); > + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); > + xinsn = SET_I_IMM(xinsn, GET_C_LW_IMM(insn)); > + break; > + case OPC_RISC_C_FUNC_FLW_LD: > + if (xlen == 32) { /* C.FLW (RV32) */ > + xinsn = OPC_RISC_FLW; > + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); > + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); > + xinsn = SET_I_IMM(xinsn, GET_C_LW_IMM(insn)); > + } else { /* C.LD (RV64/RV128) */ > + xinsn = OPC_RISC_LD; > + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); > + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); > + xinsn = SET_I_IMM(xinsn, GET_C_LD_IMM(insn)); > + } > + break; > + case OPC_RISC_C_FUNC_FSD_SQ: > + if (xlen != 128) { /* C.FSD (RV32/64) */ > + xinsn = OPC_RISC_FSD; > + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); > + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); > + xinsn = SET_S_IMM(xinsn, GET_C_SD_IMM(insn)); > + } > + break; > + case OPC_RISC_C_FUNC_SW: /* C.SW */ > + xinsn = OPC_RISC_SW; > + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); > + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); > + xinsn = SET_S_IMM(xinsn, GET_C_SW_IMM(insn)); > + break; > + case OPC_RISC_C_FUNC_FSW_SD: > + if (xlen == 32) { /* C.FSW (RV32) */ > + xinsn = OPC_RISC_FSW; > + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); > + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); > + xinsn = SET_S_IMM(xinsn, GET_C_SW_IMM(insn)); > + } else { /* C.SD (RV64/RV128) */ > + xinsn = OPC_RISC_SD; > + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); > + xinsn = SET_RS1(xinsn, GET_C_RS1S(insn)); > + xinsn = SET_S_IMM(xinsn, GET_C_SD_IMM(insn)); > + } > + break; > + default: > + break; > + } > + break; > + case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ > + switch (GET_C_FUNC(insn)) { > + case OPC_RISC_C_FUNC_FLDSP_LQSP: > + if (xlen != 128) { /* C.FLDSP (RV32/64) */ > + xinsn = OPC_RISC_FLD; > + xinsn = SET_RD(xinsn, GET_C_RD(insn)); > + xinsn = SET_RS1(xinsn, 2); > + xinsn = SET_I_IMM(xinsn, GET_C_LDSP_IMM(insn)); > + } > + break; > + case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ > + xinsn = OPC_RISC_LW; > + xinsn = SET_RD(xinsn, GET_C_RD(insn)); > + xinsn = SET_RS1(xinsn, 2); > + xinsn = SET_I_IMM(xinsn, GET_C_LWSP_IMM(insn)); > + break; > + case OPC_RISC_C_FUNC_FLWSP_LDSP: > + if (xlen == 32) { /* C.FLWSP (RV32) */ > + xinsn = OPC_RISC_FLW; > + xinsn = SET_RD(xinsn, GET_C_RD(insn)); > + xinsn = SET_RS1(xinsn, 2); > + xinsn = SET_I_IMM(xinsn, GET_C_LWSP_IMM(insn)); > + } else { /* C.LDSP (RV64/RV128) */ > + xinsn = OPC_RISC_LD; > + xinsn = SET_RD(xinsn, GET_C_RD(insn)); > + xinsn = SET_RS1(xinsn, 2); > + xinsn = SET_I_IMM(xinsn, GET_C_LDSP_IMM(insn)); > + } > + break; > + case OPC_RISC_C_FUNC_FSDSP_SQSP: > + if (xlen != 128) { /* C.FSDSP (RV32/64) */ > + xinsn = OPC_RISC_FSD; > + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); > + xinsn = SET_RS1(xinsn, 2); > + xinsn = SET_S_IMM(xinsn, GET_C_SDSP_IMM(insn)); > + } > + break; > + case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ > + xinsn = OPC_RISC_SW; > + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); > + xinsn = SET_RS1(xinsn, 2); > + xinsn = SET_S_IMM(xinsn, GET_C_SWSP_IMM(insn)); > + break; > + case 7: > + if (xlen == 32) { /* C.FSWSP (RV32) */ > + xinsn = OPC_RISC_FSW; > + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); > + xinsn = SET_RS1(xinsn, 2); > + xinsn = SET_S_IMM(xinsn, GET_C_SWSP_IMM(insn)); > + } else { /* C.SDSP (RV64/RV128) */ > + xinsn = OPC_RISC_SD; > + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); > + xinsn = SET_RS1(xinsn, 2); > + xinsn = SET_S_IMM(xinsn, GET_C_SDSP_IMM(insn)); > + } > + break; > + default: > + break; > + } > + break; > + default: > + break; > + } I don't like that we have to manually decode the instructions. As it's only a handful it's not the end of the world, but it seems like duplication that could grow. Could we not use decode_insn16() instead? That way we can share the well tested TCG decoder. Alistair > + > + /* > + * Clear Bit1 of transformed instruction to indicate that > + * original insruction was a 16bit instruction > + */ > + xinsn &= ~((target_ulong)0x2); > + } else { > + /* No need to transform 32bit (or wider) instructions */ > + xinsn = insn; > + } > + > + return xinsn; > +} > + > /* > * Handle Traps > * > @@ -842,6 +988,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) > target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; > target_ulong deleg = async ? env->mideleg : env->medeleg; > target_ulong tval = 0; > + target_ulong tinst = 0; > target_ulong htval = 0; > target_ulong mtval2 = 0; > > @@ -849,20 +996,31 @@ void riscv_cpu_do_interrupt(CPUState *cs) > /* set tval to badaddr for traps with address information */ > switch (cause) { > case RISCV_EXCP_INST_GUEST_PAGE_FAULT: > - case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: > - case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: > force_hs_execp = true; > /* fallthrough */ > case RISCV_EXCP_INST_ADDR_MIS: > case RISCV_EXCP_INST_ACCESS_FAULT: > + case RISCV_EXCP_INST_PAGE_FAULT: > + tval = env->badaddr; > + break; > + case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: > + case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: > + force_hs_execp = true; > + /* fallthrough */ > case RISCV_EXCP_LOAD_ADDR_MIS: > case RISCV_EXCP_STORE_AMO_ADDR_MIS: > case RISCV_EXCP_LOAD_ACCESS_FAULT: > case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: > - case RISCV_EXCP_INST_PAGE_FAULT: > case RISCV_EXCP_LOAD_PAGE_FAULT: > case RISCV_EXCP_STORE_PAGE_FAULT: > tval = env->badaddr; > + if (riscv_feature(env, RISCV_FEATURE_TINST)) { > +#if defined(TARGET_RISCV32) > + tinst = riscv_transformed_insn(env, 32, env->trap_insn); > +#elif defined(TARGET_RISCV64) > + tinst = riscv_transformed_insn(env, 64, env->trap_insn); > +#endif > + } > break; > case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: > case RISCV_EXCP_ILLEGAL_INST: > @@ -955,6 +1113,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) > env->sepc = env->pc; > env->sbadaddr = tval; > env->htval = htval; > + env->htinst = tinst; > env->pc = (env->stvec >> 2 << 2) + > ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); > riscv_cpu_set_mode(env, PRV_S); > @@ -994,6 +1153,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) > env->mepc = env->pc; > env->mbadaddr = tval; > env->mtval2 = mtval2; > + env->mtinst = tinst; > env->pc = (env->mtvec >> 2 << 2) + > ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); > riscv_cpu_set_mode(env, PRV_M); > diff --git a/target/riscv/instmap.h b/target/riscv/instmap.h > index 40b6d2b64d..f4ee686c78 100644 > --- a/target/riscv/instmap.h > +++ b/target/riscv/instmap.h > @@ -316,6 +316,12 @@ enum { > #define GET_RS2(inst) extract32(inst, 20, 5) > #define GET_RD(inst) extract32(inst, 7, 5) > #define GET_IMM(inst) sextract64(inst, 20, 12) > +#define SET_RS1(inst, val) deposit32(inst, 15, 5, val) > +#define SET_RS2(inst, val) deposit32(inst, 20, 5, val) > +#define SET_RD(inst, val) deposit32(inst, 7, 5, val) > +#define SET_I_IMM(inst, val) deposit32(inst, 20, 12, val) > +#define SET_S_IMM(inst, val) \ > + deposit32(deposit32(inst, 7, 5, val), 25, 7, (val) >> 5) > > /* RVC decoding macros */ > #define GET_C_IMM(inst) (extract32(inst, 2, 5) \ > @@ -346,6 +352,8 @@ enum { > | (extract32(inst, 5, 1) << 6)) > #define GET_C_LD_IMM(inst) ((extract16(inst, 10, 3) << 3) \ > | (extract16(inst, 5, 2) << 6)) > +#define GET_C_SW_IMM(inst) GET_C_LW_IMM(inst) > +#define GET_C_SD_IMM(inst) GET_C_LD_IMM(inst) > #define GET_C_J_IMM(inst) ((extract32(inst, 3, 3) << 1) \ > | (extract32(inst, 11, 1) << 4) \ > | (extract32(inst, 2, 1) << 5) \ > @@ -366,4 +374,37 @@ enum { > #define GET_C_RS1S(inst) (8 + extract16(inst, 7, 3)) > #define GET_C_RS2S(inst) (8 + extract16(inst, 2, 3)) > > +#define GET_C_FUNC(inst) extract32(inst, 13, 3) > +#define GET_C_OP(inst) extract32(inst, 0, 2) > + > +enum { > + /* RVC Quadrants */ > + OPC_RISC_C_OP_QUAD0 = 0x0, > + OPC_RISC_C_OP_QUAD1 = 0x1, > + OPC_RISC_C_OP_QUAD2 = 0x2 > +}; > + > +enum { > + /* RVC Quadrant 0 */ > + OPC_RISC_C_FUNC_ADDI4SPN = 0x0, > + OPC_RISC_C_FUNC_FLD_LQ = 0x1, > + OPC_RISC_C_FUNC_LW = 0x2, > + OPC_RISC_C_FUNC_FLW_LD = 0x3, > + OPC_RISC_C_FUNC_FSD_SQ = 0x5, > + OPC_RISC_C_FUNC_SW = 0x6, > + OPC_RISC_C_FUNC_FSW_SD = 0x7 > +}; > + > +enum { > + /* RVC Quadrant 2 */ > + OPC_RISC_C_FUNC_SLLI_SLLI64 = 0x0, > + OPC_RISC_C_FUNC_FLDSP_LQSP = 0x1, > + OPC_RISC_C_FUNC_LWSP = 0x2, > + OPC_RISC_C_FUNC_FLWSP_LDSP = 0x3, > + OPC_RISC_C_FUNC_JR_MV_EBREAK_JALR_ADD = 0x4, > + OPC_RISC_C_FUNC_FSDSP_SQSP = 0x5, > + OPC_RISC_C_FUNC_SWSP = 0x6, > + OPC_RISC_C_FUNC_FSWSP_SDSP = 0x7 > +}; > + > #endif > -- > 2.25.1 > > ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt() 2020-08-12 23:16 ` Alistair Francis @ 2020-08-13 15:52 ` Richard Henderson 0 siblings, 0 replies; 8+ messages in thread From: Richard Henderson @ 2020-08-13 15:52 UTC (permalink / raw) To: Alistair Francis, Anup Patel Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel, qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis, Palmer Dabbelt On 8/12/20 4:16 PM, Alistair Francis wrote: > I don't like that we have to manually decode the instructions. As it's > only a handful it's not the end of the world, but it seems like > duplication that could grow. Could we not use decode_insn16() instead? > That way we can share the well tested TCG decoder. Certainly. Compare how the decoder can be re-purposed for disassembly -- e.g. target/openrisc/disas.c. Perhaps something like typedef uint32_t DisasContext; #include "decode_insn16.inc.c" /* * This function is supposed to be called for an instruction * that has already executed, and thus is known to be valid. * That said, return 0 for an invalid instruction. */ uint32_t riscv_expand_rvc_to_rvi(uint16_t insn16) { uint32_t insn32 = 0; /* illegal instruction */ decode_insn16(&insn32, insn16); return insn32; } static bool expand_i(DisasContext *ctx, arg_immi *a, uint32_t insn32) { insn32 = SET_RD(insn32, a->rd); insn32 = SET_RS1(insn32, a->rs1); insn32 = SET_I_IMM(insn32, a->imm); *ctx = insn32; return true; } static bool trans_addi(DisasContext *ctx, arg_immi *a) { return expand_i(ctx, a, OPC_RISC_ADDI); } etc. All placed in a new file, so that the myriad symbols don't conflict with anything else. r~ ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-08-13 15:53 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-07-29 11:27 [PATCH 0/3] Trapped instruction encoding support Anup Patel 2020-07-29 11:27 ` [PATCH 1/3] target/riscv: Optional feature to provide trapped instruction in CSRs Anup Patel 2020-08-12 22:37 ` Alistair Francis 2020-07-29 11:28 ` [PATCH 2/3] target/riscv: Fix write_htinst() implementation Anup Patel 2020-08-10 22:37 ` Alistair Francis 2020-07-29 11:28 ` [PATCH 3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt() Anup Patel 2020-08-12 23:16 ` Alistair Francis 2020-08-13 15:52 ` Richard Henderson
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