From: Alistair Francis <alistair23@gmail.com>
To: "~eopxd" <yueh.ting.chen@gmail.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Frank Chang <frank.chang@sifive.com>,
WeiWei Li <liweiwei@iscas.ac.cn>, eop Chen <eop.chen@sifive.com>
Subject: Re: [PATCH qemu v6 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions
Date: Thu, 21 Jul 2022 10:13:38 +1000 [thread overview]
Message-ID: <CAKmqyKMCmRyQtqvbyLOxOYNhAh-6uWeSD4kRgccM_MJ7zy8a=g@mail.gmail.com> (raw)
In-Reply-To: <165570784143.17634.35095816584573691-4@git.sr.ht>
On Mon, Jun 20, 2022 at 4:52 PM ~eopxd <eopxd@git.sr.ht> wrote:
>
> From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 1 +
> target/riscv/vector_helper.c | 7 +++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 07d86551a9..83b85bb851 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1901,6 +1901,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> data = FIELD_DP32(data, VDATA, VTA, s->vta); \
> + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs1), \
> vreg_ofs(s, a->rs2), cpu_env, \
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 6be3c4e739..d1daa764b7 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -1298,10 +1298,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
> uint32_t esz = sizeof(TS1); \
> uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
> continue; \
> } \
> TS1 s1 = *((TS1 *)vs1 + HS1(i)); \
> @@ -1339,10 +1342,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
> uint32_t total_elems = \
> vext_get_total_elems(env, desc, esz); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * esz, \
> + (i + 1) * esz); \
> continue; \
> } \
> TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
> --
> 2.34.2
>
>
next prev parent reply other threads:[~2022-07-21 0:14 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-20 6:50 [PATCH qemu v6 00/10] Add mask agnostic behavior for rvv instructions ~eopxd
2022-03-17 7:26 ` [PATCH qemu v6 01/10] target/riscv: rvv: Add mask agnostic for vv instructions ~eopxd
2022-07-21 0:09 ` Alistair Francis
2022-03-17 7:47 ` [PATCH qemu v6 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions ~eopxd
2022-07-21 0:11 ` Alistair Francis
2022-03-17 8:38 ` [PATCH qemu v6 03/10] target/riscv: rvv: Add mask agnostic for vx instructions ~eopxd
2022-07-21 0:12 ` Alistair Francis
2022-03-17 8:43 ` [PATCH qemu v6 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions ~eopxd
2022-07-21 0:13 ` Alistair Francis [this message]
2022-03-17 8:46 ` [PATCH qemu v6 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions ~eopxd
2022-07-21 0:16 ` Alistair Francis
2022-03-17 8:52 ` [PATCH qemu v6 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions ~eopxd
2022-07-21 0:20 ` Alistair Francis
2022-03-17 9:08 ` [PATCH qemu v6 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions ~eopxd
2022-07-21 0:21 ` Alistair Francis
2022-03-17 9:14 ` [PATCH qemu v6 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions ~eopxd
2022-07-21 0:22 ` Alistair Francis
2022-03-17 9:32 ` [PATCH qemu v6 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions ~eopxd
2022-07-21 0:23 ` Alistair Francis
2022-05-10 18:10 ` [PATCH qemu v6 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior ~eopxd
2022-07-21 0:24 ` Alistair Francis
2022-07-11 7:07 ` [PATCH qemu v6 00/10] Add mask agnostic behavior for rvv instructions eop Chen
2022-07-21 2:31 ` Alistair Francis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAKmqyKMCmRyQtqvbyLOxOYNhAh-6uWeSD4kRgccM_MJ7zy8a=g@mail.gmail.com' \
--to=alistair23@gmail.com \
--cc=alistair.francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=eop.chen@sifive.com \
--cc=frank.chang@sifive.com \
--cc=liweiwei@iscas.ac.cn \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=yueh.ting.chen@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).