[PATCH 0/4] target/riscv: Some CPURISCVState related cleanup and simplification

[PATCH 0/4] target/riscv: Some CPURISCVState related cleanup and simplification

[Weiwei Li]

The patchset tries to:

- Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.
- Use env_archcpu() to get RISCVCPU pointer from env directly
- Use CPURISCVState as argument directly in riscv_cpu_update_mip and riscv_timer_write_timecmp to simplify type conversion
- Remove RISCVCPU argument of riscv_csrrw_check, and get cfg infomation from CPURISCVState directly

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-cleanup-upstream

Weiwei Li (4):
  target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
  target/riscv: Simplify getting RISCVCPU pointer from env
  target/riscv: Simplify type conversion for CPURISCVState
  target/riscv: Simplify arguments for riscv_csrrw_check

 target/riscv/cpu.c         |  6 +--
 target/riscv/cpu.h         |  3 +-
 target/riscv/cpu_helper.c  | 17 ++++----
 target/riscv/csr.c         | 87 ++++++++++++--------------------------
 target/riscv/gdbstub.c     |  4 +-
 target/riscv/pmu.c         | 14 +++---
 target/riscv/time_helper.c | 15 +++----
 target/riscv/time_helper.h |  2 +-
 8 files changed, 57 insertions(+), 91 deletions(-)

-- 
2.25.1

[PATCH 1/4] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig

[Weiwei Li]

Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu_helper.c |  9 ++++-----
 target/riscv/csr.c        | 40 ++++++++++++---------------------------
 target/riscv/gdbstub.c    |  4 ++--
 3 files changed, 18 insertions(+), 35 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f88c503cf4..e677255f87 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -314,7 +314,6 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
                                     int extirq, unsigned int extirq_def_prio,
                                     uint64_t pending, uint8_t *iprio)
 {
-    RISCVCPU *cpu = env_archcpu(env);
     int irq, best_irq = RISCV_EXCP_NONE;
     unsigned int prio, best_prio = UINT_MAX;
 
@@ -323,7 +322,8 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
     }
 
     irq = ctz64(pending);
-    if (!((extirq == IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ssaia)) {
+    if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia :
+                                  riscv_cpu_cfg(env)->ext_ssaia)) {
         return irq;
     }
 
@@ -765,7 +765,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
     int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
     bool use_background = false;
     hwaddr ppn;
-    RISCVCPU *cpu = env_archcpu(env);
     int napot_bits = 0;
     target_ulong napot_mask;
 
@@ -946,7 +945,7 @@ restart:
 
         if (riscv_cpu_sxl(env) == MXL_RV32) {
             ppn = pte >> PTE_PPN_SHIFT;
-        } else if (pbmte || cpu->cfg.ext_svnapot) {
+        } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) {
             ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
         } else {
             ppn = pte >> PTE_PPN_SHIFT;
@@ -1043,7 +1042,7 @@ restart:
                benefit. */
             target_ulong vpn = addr >> PGSHIFT;
 
-            if (cpu->cfg.ext_svnapot && (pte & PTE_N)) {
+            if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
                 napot_bits = ctzl(ppn) + 1;
                 if ((i != (levels - 1)) || (napot_bits != 4)) {
                     return TRANSLATE_FAIL;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ab566639e5..b453d8e8ca 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -88,9 +88,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
-    if (cpu->cfg.ext_zve32f) {
+    if (riscv_cpu_cfg(env)->ext_zve32f) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
@@ -193,9 +191,7 @@ static RISCVException mctr32(CPURISCVState *env, int csrno)
 
 static RISCVException sscofpmf(CPURISCVState *env, int csrno)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
-    if (!cpu->cfg.ext_sscofpmf) {
+    if (!riscv_cpu_cfg(env)->ext_sscofpmf) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -310,9 +306,7 @@ static RISCVException umode32(CPURISCVState *env, int csrno)
 
 static RISCVException mstateen(CPURISCVState *env, int csrno)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
-    if (!cpu->cfg.ext_smstateen) {
+    if (!riscv_cpu_cfg(env)->ext_smstateen) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -321,9 +315,7 @@ static RISCVException mstateen(CPURISCVState *env, int csrno)
 
 static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
-    if (!cpu->cfg.ext_smstateen) {
+    if (!riscv_cpu_cfg(env)->ext_smstateen) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -390,10 +382,9 @@ static RISCVException sstateen(CPURISCVState *env, int csrno)
 
 static RISCVException sstc(CPURISCVState *env, int csrno)
 {
-    RISCVCPU *cpu = env_archcpu(env);
     bool hmode_check = false;
 
-    if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
+    if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -1170,27 +1161,21 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
 static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
                                      target_ulong *val)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
-    *val = cpu->cfg.mvendorid;
+    *val = riscv_cpu_cfg(env)->mvendorid;
     return RISCV_EXCP_NONE;
 }
 
 static RISCVException read_marchid(CPURISCVState *env, int csrno,
                                    target_ulong *val)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
-    *val = cpu->cfg.marchid;
+    *val = riscv_cpu_cfg(env)->marchid;
     return RISCV_EXCP_NONE;
 }
 
 static RISCVException read_mimpid(CPURISCVState *env, int csrno,
                                   target_ulong *val)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
-    *val = cpu->cfg.mimpid;
+    *val = riscv_cpu_cfg(env)->mimpid;
     return RISCV_EXCP_NONE;
 }
 
@@ -1232,9 +1217,8 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
 
 static bool validate_vm(CPURISCVState *env, target_ulong vm)
 {
-    RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
-
-    return (vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map);
+    return (vm & 0xf) <=
+           satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map);
 }
 
 static RISCVException write_mstatus(CPURISCVState *env, int csrno,
@@ -1897,7 +1881,7 @@ static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
 static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
                                     target_ulong val)
 {
-    RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
+    const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
     uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
 
     if (riscv_cpu_mxl(env) == MXL_RV64) {
@@ -1920,7 +1904,7 @@ static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
 static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
                                      target_ulong val)
 {
-    RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
+    const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
     uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
                     (cfg->ext_sstc ? MENVCFG_STCE : 0) |
                     (cfg->ext_svadu ? MENVCFG_HADE : 0);
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 6048541606..b2e08f1979 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -129,7 +129,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
 
 static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
 {
-    uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+    uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
     if (n < 32) {
         int i;
         int cnt = 0;
@@ -145,7 +145,7 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
 
 static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
 {
-    uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+    uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
     if (n < 32) {
         int i;
         for (i = 0; i < vlenb; i += 8) {
-- 
2.25.1

Re: [PATCH 1/4] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig

[Daniel Henrique Barboza]

On 3/9/23 04:13, Weiwei Li wrote:
> Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu_helper.c |  9 ++++-----
>   target/riscv/csr.c        | 40 ++++++++++++---------------------------
>   target/riscv/gdbstub.c    |  4 ++--
>   3 files changed, 18 insertions(+), 35 deletions(-)
> 
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index f88c503cf4..e677255f87 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -314,7 +314,6 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
>                                       int extirq, unsigned int extirq_def_prio,
>                                       uint64_t pending, uint8_t *iprio)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
>       int irq, best_irq = RISCV_EXCP_NONE;
>       unsigned int prio, best_prio = UINT_MAX;
>   
> @@ -323,7 +322,8 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
>       }
>   
>       irq = ctz64(pending);
> -    if (!((extirq == IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ssaia)) {
> +    if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia :
> +                                  riscv_cpu_cfg(env)->ext_ssaia)) {
>           return irq;
>       }
>   
> @@ -765,7 +765,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
>       int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
>       bool use_background = false;
>       hwaddr ppn;
> -    RISCVCPU *cpu = env_archcpu(env);
>       int napot_bits = 0;
>       target_ulong napot_mask;
>   
> @@ -946,7 +945,7 @@ restart:
>   
>           if (riscv_cpu_sxl(env) == MXL_RV32) {
>               ppn = pte >> PTE_PPN_SHIFT;
> -        } else if (pbmte || cpu->cfg.ext_svnapot) {
> +        } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) {
>               ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
>           } else {
>               ppn = pte >> PTE_PPN_SHIFT;
> @@ -1043,7 +1042,7 @@ restart:
>                  benefit. */
>               target_ulong vpn = addr >> PGSHIFT;
>   
> -            if (cpu->cfg.ext_svnapot && (pte & PTE_N)) {
> +            if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
>                   napot_bits = ctzl(ppn) + 1;
>                   if ((i != (levels - 1)) || (napot_bits != 4)) {
>                       return TRANSLATE_FAIL;
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index ab566639e5..b453d8e8ca 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -88,9 +88,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
>   
>   static RISCVException vs(CPURISCVState *env, int csrno)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    if (cpu->cfg.ext_zve32f) {
> +    if (riscv_cpu_cfg(env)->ext_zve32f) {
>   #if !defined(CONFIG_USER_ONLY)
>           if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
>               return RISCV_EXCP_ILLEGAL_INST;
> @@ -193,9 +191,7 @@ static RISCVException mctr32(CPURISCVState *env, int csrno)
>   
>   static RISCVException sscofpmf(CPURISCVState *env, int csrno)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    if (!cpu->cfg.ext_sscofpmf) {
> +    if (!riscv_cpu_cfg(env)->ext_sscofpmf) {
>           return RISCV_EXCP_ILLEGAL_INST;
>       }
>   
> @@ -310,9 +306,7 @@ static RISCVException umode32(CPURISCVState *env, int csrno)
>   
>   static RISCVException mstateen(CPURISCVState *env, int csrno)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    if (!cpu->cfg.ext_smstateen) {
> +    if (!riscv_cpu_cfg(env)->ext_smstateen) {
>           return RISCV_EXCP_ILLEGAL_INST;
>       }
>   
> @@ -321,9 +315,7 @@ static RISCVException mstateen(CPURISCVState *env, int csrno)
>   
>   static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    if (!cpu->cfg.ext_smstateen) {
> +    if (!riscv_cpu_cfg(env)->ext_smstateen) {
>           return RISCV_EXCP_ILLEGAL_INST;
>       }
>   
> @@ -390,10 +382,9 @@ static RISCVException sstateen(CPURISCVState *env, int csrno)
>   
>   static RISCVException sstc(CPURISCVState *env, int csrno)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
>       bool hmode_check = false;
>   
> -    if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
> +    if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) {
>           return RISCV_EXCP_ILLEGAL_INST;
>       }
>   
> @@ -1170,27 +1161,21 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
>   static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
>                                        target_ulong *val)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    *val = cpu->cfg.mvendorid;
> +    *val = riscv_cpu_cfg(env)->mvendorid;
>       return RISCV_EXCP_NONE;
>   }
>   
>   static RISCVException read_marchid(CPURISCVState *env, int csrno,
>                                      target_ulong *val)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    *val = cpu->cfg.marchid;
> +    *val = riscv_cpu_cfg(env)->marchid;
>       return RISCV_EXCP_NONE;
>   }
>   
>   static RISCVException read_mimpid(CPURISCVState *env, int csrno,
>                                     target_ulong *val)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    *val = cpu->cfg.mimpid;
> +    *val = riscv_cpu_cfg(env)->mimpid;
>       return RISCV_EXCP_NONE;
>   }
>   
> @@ -1232,9 +1217,8 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
>   
>   static bool validate_vm(CPURISCVState *env, target_ulong vm)
>   {
> -    RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
> -
> -    return (vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map);
> +    return (vm & 0xf) <=
> +           satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map);
>   }
>   
>   static RISCVException write_mstatus(CPURISCVState *env, int csrno,
> @@ -1897,7 +1881,7 @@ static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
>   static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
>                                       target_ulong val)
>   {
> -    RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
> +    const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
>       uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
>   
>       if (riscv_cpu_mxl(env) == MXL_RV64) {
> @@ -1920,7 +1904,7 @@ static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
>   static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
>                                        target_ulong val)
>   {
> -    RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
> +    const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
>       uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
>                       (cfg->ext_sstc ? MENVCFG_STCE : 0) |
>                       (cfg->ext_svadu ? MENVCFG_HADE : 0);
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 6048541606..b2e08f1979 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -129,7 +129,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
>   
>   static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
>   {
> -    uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
> +    uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
>       if (n < 32) {
>           int i;
>           int cnt = 0;
> @@ -145,7 +145,7 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
>   
>   static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
>   {
> -    uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
> +    uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
>       if (n < 32) {
>           int i;
>           for (i = 0; i < vlenb; i += 8) {

Re: [PATCH 1/4] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig

[Alistair Francis]

On Thu, Mar 9, 2023 at 5:14 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_helper.c |  9 ++++-----
>  target/riscv/csr.c        | 40 ++++++++++++---------------------------
>  target/riscv/gdbstub.c    |  4 ++--
>  3 files changed, 18 insertions(+), 35 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index f88c503cf4..e677255f87 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -314,7 +314,6 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
>                                      int extirq, unsigned int extirq_def_prio,
>                                      uint64_t pending, uint8_t *iprio)
>  {
> -    RISCVCPU *cpu = env_archcpu(env);
>      int irq, best_irq = RISCV_EXCP_NONE;
>      unsigned int prio, best_prio = UINT_MAX;
>
> @@ -323,7 +322,8 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
>      }
>
>      irq = ctz64(pending);
> -    if (!((extirq == IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ssaia)) {
> +    if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia :
> +                                  riscv_cpu_cfg(env)->ext_ssaia)) {
>          return irq;
>      }
>
> @@ -765,7 +765,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
>      int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
>      bool use_background = false;
>      hwaddr ppn;
> -    RISCVCPU *cpu = env_archcpu(env);
>      int napot_bits = 0;
>      target_ulong napot_mask;
>
> @@ -946,7 +945,7 @@ restart:
>
>          if (riscv_cpu_sxl(env) == MXL_RV32) {
>              ppn = pte >> PTE_PPN_SHIFT;
> -        } else if (pbmte || cpu->cfg.ext_svnapot) {
> +        } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) {
>              ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
>          } else {
>              ppn = pte >> PTE_PPN_SHIFT;
> @@ -1043,7 +1042,7 @@ restart:
>                 benefit. */
>              target_ulong vpn = addr >> PGSHIFT;
>
> -            if (cpu->cfg.ext_svnapot && (pte & PTE_N)) {
> +            if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
>                  napot_bits = ctzl(ppn) + 1;
>                  if ((i != (levels - 1)) || (napot_bits != 4)) {
>                      return TRANSLATE_FAIL;
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index ab566639e5..b453d8e8ca 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -88,9 +88,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
>
>  static RISCVException vs(CPURISCVState *env, int csrno)
>  {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    if (cpu->cfg.ext_zve32f) {
> +    if (riscv_cpu_cfg(env)->ext_zve32f) {
>  #if !defined(CONFIG_USER_ONLY)
>          if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
>              return RISCV_EXCP_ILLEGAL_INST;
> @@ -193,9 +191,7 @@ static RISCVException mctr32(CPURISCVState *env, int csrno)
>
>  static RISCVException sscofpmf(CPURISCVState *env, int csrno)
>  {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    if (!cpu->cfg.ext_sscofpmf) {
> +    if (!riscv_cpu_cfg(env)->ext_sscofpmf) {
>          return RISCV_EXCP_ILLEGAL_INST;
>      }
>
> @@ -310,9 +306,7 @@ static RISCVException umode32(CPURISCVState *env, int csrno)
>
>  static RISCVException mstateen(CPURISCVState *env, int csrno)
>  {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    if (!cpu->cfg.ext_smstateen) {
> +    if (!riscv_cpu_cfg(env)->ext_smstateen) {
>          return RISCV_EXCP_ILLEGAL_INST;
>      }
>
> @@ -321,9 +315,7 @@ static RISCVException mstateen(CPURISCVState *env, int csrno)
>
>  static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
>  {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    if (!cpu->cfg.ext_smstateen) {
> +    if (!riscv_cpu_cfg(env)->ext_smstateen) {
>          return RISCV_EXCP_ILLEGAL_INST;
>      }
>
> @@ -390,10 +382,9 @@ static RISCVException sstateen(CPURISCVState *env, int csrno)
>
>  static RISCVException sstc(CPURISCVState *env, int csrno)
>  {
> -    RISCVCPU *cpu = env_archcpu(env);
>      bool hmode_check = false;
>
> -    if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
> +    if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) {
>          return RISCV_EXCP_ILLEGAL_INST;
>      }
>
> @@ -1170,27 +1161,21 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
>  static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
>                                       target_ulong *val)
>  {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    *val = cpu->cfg.mvendorid;
> +    *val = riscv_cpu_cfg(env)->mvendorid;
>      return RISCV_EXCP_NONE;
>  }
>
>  static RISCVException read_marchid(CPURISCVState *env, int csrno,
>                                     target_ulong *val)
>  {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    *val = cpu->cfg.marchid;
> +    *val = riscv_cpu_cfg(env)->marchid;
>      return RISCV_EXCP_NONE;
>  }
>
>  static RISCVException read_mimpid(CPURISCVState *env, int csrno,
>                                    target_ulong *val)
>  {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    *val = cpu->cfg.mimpid;
> +    *val = riscv_cpu_cfg(env)->mimpid;
>      return RISCV_EXCP_NONE;
>  }
>
> @@ -1232,9 +1217,8 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
>
>  static bool validate_vm(CPURISCVState *env, target_ulong vm)
>  {
> -    RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
> -
> -    return (vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map);
> +    return (vm & 0xf) <=
> +           satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map);
>  }
>
>  static RISCVException write_mstatus(CPURISCVState *env, int csrno,
> @@ -1897,7 +1881,7 @@ static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
>  static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
>                                      target_ulong val)
>  {
> -    RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
> +    const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
>      uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
>
>      if (riscv_cpu_mxl(env) == MXL_RV64) {
> @@ -1920,7 +1904,7 @@ static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
>  static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
>                                       target_ulong val)
>  {
> -    RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
> +    const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
>      uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
>                      (cfg->ext_sstc ? MENVCFG_STCE : 0) |
>                      (cfg->ext_svadu ? MENVCFG_HADE : 0);
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 6048541606..b2e08f1979 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -129,7 +129,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
>
>  static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
>  {
> -    uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
> +    uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
>      if (n < 32) {
>          int i;
>          int cnt = 0;
> @@ -145,7 +145,7 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
>
>  static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
>  {
> -    uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
> +    uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
>      if (n < 32) {
>          int i;
>          for (i = 0; i < vlenb; i += 8) {
> --
> 2.25.1
>
>

[PATCH 2/4] target/riscv: Simplify getting RISCVCPU pointer from env

[Weiwei Li]

Use env_archcpu() to get RISCVCPU pointer from env directly.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/pmu.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index b8e56d2b7b..a200741083 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -223,7 +223,7 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
         return true;
     }
 
-    cpu = RISCV_CPU(env_cpu(env));
+    cpu = env_archcpu(env);
     if (!cpu->pmu_event_ctr_map) {
         return false;
     }
@@ -249,7 +249,7 @@ bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr)
         return true;
     }
 
-    cpu = RISCV_CPU(env_cpu(env));
+    cpu = env_archcpu(env);
     if (!cpu->pmu_event_ctr_map) {
         return false;
     }
@@ -289,7 +289,7 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
                                uint32_t ctr_idx)
 {
     uint32_t event_idx;
-    RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
+    RISCVCPU *cpu = env_archcpu(env);
 
     if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map) {
         return -1;
@@ -390,7 +390,7 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx)
 {
     uint64_t overflow_delta, overflow_at;
     int64_t overflow_ns, overflow_left = 0;
-    RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
+    RISCVCPU *cpu = env_archcpu(env);
     PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
 
     if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf) {
-- 
2.25.1

Re: [PATCH 2/4] target/riscv: Simplify getting RISCVCPU pointer from env

[Daniel Henrique Barboza]

On 3/9/23 04:13, Weiwei Li wrote:
> Use env_archcpu() to get RISCVCPU pointer from env directly.
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/pmu.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
> index b8e56d2b7b..a200741083 100644
> --- a/target/riscv/pmu.c
> +++ b/target/riscv/pmu.c
> @@ -223,7 +223,7 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
>           return true;
>       }
>   
> -    cpu = RISCV_CPU(env_cpu(env));
> +    cpu = env_archcpu(env);
>       if (!cpu->pmu_event_ctr_map) {
>           return false;
>       }
> @@ -249,7 +249,7 @@ bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr)
>           return true;
>       }
>   
> -    cpu = RISCV_CPU(env_cpu(env));
> +    cpu = env_archcpu(env);
>       if (!cpu->pmu_event_ctr_map) {
>           return false;
>       }
> @@ -289,7 +289,7 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
>                                  uint32_t ctr_idx)
>   {
>       uint32_t event_idx;
> -    RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
> +    RISCVCPU *cpu = env_archcpu(env);
>   
>       if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map) {
>           return -1;
> @@ -390,7 +390,7 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx)
>   {
>       uint64_t overflow_delta, overflow_at;
>       int64_t overflow_ns, overflow_left = 0;
> -    RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
> +    RISCVCPU *cpu = env_archcpu(env);
>       PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
>   
>       if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf) {

Re: [PATCH 2/4] target/riscv: Simplify getting RISCVCPU pointer from env

[Alistair Francis]

On Thu, Mar 9, 2023 at 5:14 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Use env_archcpu() to get RISCVCPU pointer from env directly.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/pmu.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
> index b8e56d2b7b..a200741083 100644
> --- a/target/riscv/pmu.c
> +++ b/target/riscv/pmu.c
> @@ -223,7 +223,7 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
>          return true;
>      }
>
> -    cpu = RISCV_CPU(env_cpu(env));
> +    cpu = env_archcpu(env);
>      if (!cpu->pmu_event_ctr_map) {
>          return false;
>      }
> @@ -249,7 +249,7 @@ bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr)
>          return true;
>      }
>
> -    cpu = RISCV_CPU(env_cpu(env));
> +    cpu = env_archcpu(env);
>      if (!cpu->pmu_event_ctr_map) {
>          return false;
>      }
> @@ -289,7 +289,7 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
>                                 uint32_t ctr_idx)
>  {
>      uint32_t event_idx;
> -    RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
> +    RISCVCPU *cpu = env_archcpu(env);
>
>      if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map) {
>          return -1;
> @@ -390,7 +390,7 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx)
>  {
>      uint64_t overflow_delta, overflow_at;
>      int64_t overflow_ns, overflow_left = 0;
> -    RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
> +    RISCVCPU *cpu = env_archcpu(env);
>      PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
>
>      if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf) {
> --
> 2.25.1
>
>

Re: [PATCH 2/4] target/riscv: Simplify getting RISCVCPU pointer from env

[Philippe Mathieu-Daudé]

On 9/3/23 08:13, Weiwei Li wrote:
> Use env_archcpu() to get RISCVCPU pointer from env directly.
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/pmu.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

[PATCH 3/4] target/riscv: Simplify type conversion for CPURISCVState

[Weiwei Li]

Use CPURISCVState as argument directly in riscv_cpu_update_mip and
riscv_timer_write_timecmp, since type converts from CPURISCVState to
RISCVCPU in many caller of them and then back to CPURISCVState in them.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.c         |  6 +++---
 target/riscv/cpu.h         |  3 ++-
 target/riscv/cpu_helper.c  |  8 ++++----
 target/riscv/csr.c         | 35 +++++++++++------------------------
 target/riscv/pmu.c         |  6 +++---
 target/riscv/time_helper.c | 15 +++++++--------
 target/riscv/time_helper.h |  2 +-
 7 files changed, 31 insertions(+), 44 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e97473af2..16e465a0ab 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1302,7 +1302,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
             if (kvm_enabled()) {
                 kvm_riscv_set_irq(cpu, irq, level);
             } else {
-                riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
+                riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level));
             }
              break;
         case IRQ_S_EXT:
@@ -1310,7 +1310,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
                 kvm_riscv_set_irq(cpu, irq, level);
             } else {
                 env->external_seip = level;
-                riscv_cpu_update_mip(cpu, 1 << irq,
+                riscv_cpu_update_mip(env, 1 << irq,
                                      BOOL_TO_MASK(level | env->software_seip));
             }
             break;
@@ -1336,7 +1336,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
         }
 
         /* Update mip.SGEIP bit */
-        riscv_cpu_update_mip(cpu, MIP_SGEIP,
+        riscv_cpu_update_mip(env, MIP_SGEIP,
                              BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
     } else {
         g_assert_not_reached();
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 638e47c75a..5adefe4ab5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -602,7 +602,8 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
-uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
+uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
+                              uint64_t value);
 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
                              void *arg);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e677255f87..824f0cbd92 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -590,7 +590,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
          *
          * To solve this, we check and inject interrupt after setting V=1.
          */
-        riscv_cpu_update_mip(env_archcpu(env), 0, 0);
+        riscv_cpu_update_mip(env, 0, 0);
     }
 }
 
@@ -610,10 +610,10 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
     }
 }
 
-uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
+uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
+                              uint64_t value)
 {
-    CPURISCVState *env = &cpu->env;
-    CPUState *cs = CPU(cpu);
+    CPUState *cs = env_cpu(env);
     uint64_t gein, vsgein = 0, vstip = 0, old = env->mip;
 
     if (riscv_cpu_virt_enabled(env)) {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index b453d8e8ca..53143f4d9a 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -990,15 +990,13 @@ static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
 static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
                                       target_ulong val)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
     if (riscv_cpu_mxl(env) == MXL_RV32) {
         env->vstimecmp = deposit64(env->vstimecmp, 0, 32, (uint64_t)val);
     } else {
         env->vstimecmp = val;
     }
 
-    riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+    riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
                               env->htimedelta, MIP_VSTIP);
 
     return RISCV_EXCP_NONE;
@@ -1007,10 +1005,8 @@ static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
 static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
                                        target_ulong val)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
     env->vstimecmp = deposit64(env->vstimecmp, 32, 32, (uint64_t)val);
-    riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+    riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
                               env->htimedelta, MIP_VSTIP);
 
     return RISCV_EXCP_NONE;
@@ -1043,8 +1039,6 @@ static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
 static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
                                      target_ulong val)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
     if (riscv_cpu_virt_enabled(env)) {
         if (env->hvictl & HVICTL_VTI) {
             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
@@ -1058,7 +1052,7 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
         env->stimecmp = val;
     }
 
-    riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP);
+    riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
 
     return RISCV_EXCP_NONE;
 }
@@ -1066,8 +1060,6 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
 static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
                                       target_ulong val)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
     if (riscv_cpu_virt_enabled(env)) {
         if (env->hvictl & HVICTL_VTI) {
             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
@@ -1076,7 +1068,7 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
     }
 
     env->stimecmp = deposit64(env->stimecmp, 32, 32, (uint64_t)val);
-    riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP);
+    riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
 
     return RISCV_EXCP_NONE;
 }
@@ -2211,7 +2203,6 @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
                                 uint64_t *ret_val,
                                 uint64_t new_val, uint64_t wr_mask)
 {
-    RISCVCPU *cpu = env_archcpu(env);
     uint64_t old_mip, mask = wr_mask & delegable_ints;
     uint32_t gin;
 
@@ -2220,14 +2211,14 @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
         new_val |= env->external_seip * MIP_SEIP;
     }
 
-    if (cpu->cfg.ext_sstc && (env->priv == PRV_M) &&
+    if (riscv_cpu_cfg(env)->ext_sstc && (env->priv == PRV_M) &&
         get_field(env->menvcfg, MENVCFG_STCE)) {
         /* sstc extension forbids STIP & VSTIP to be writeable in mip */
         mask = mask & ~(MIP_STIP | MIP_VSTIP);
     }
 
     if (mask) {
-        old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask));
+        old_mip = riscv_cpu_update_mip(env, mask, (new_val & mask));
     } else {
         old_mip = env->mip;
     }
@@ -2987,7 +2978,7 @@ static RISCVException write_hgeie(CPURISCVState *env, int csrno,
     val &= ((((target_ulong)1) << env->geilen) - 1) << 1;
     env->hgeie = val;
     /* Update mip.SGEIP bit */
-    riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP,
+    riscv_cpu_update_mip(env, MIP_SGEIP,
                          BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
     return RISCV_EXCP_NONE;
 }
@@ -3056,8 +3047,6 @@ static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
 static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
                                        target_ulong val)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
     if (!env->rdtime_fn) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
@@ -3068,8 +3057,8 @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
         env->htimedelta = val;
     }
 
-    if (cpu->cfg.ext_sstc && env->rdtime_fn) {
-        riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+    if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) {
+        riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
                                   env->htimedelta, MIP_VSTIP);
     }
 
@@ -3090,16 +3079,14 @@ static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
                                         target_ulong val)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
     if (!env->rdtime_fn) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
 
-    if (cpu->cfg.ext_sstc && env->rdtime_fn) {
-        riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+    if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) {
+        riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
                                   env->htimedelta, MIP_VSTIP);
     }
 
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index a200741083..22e2283c76 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -133,7 +133,7 @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx)
             /* Generate interrupt only if OF bit is clear */
             if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) {
                 env->mhpmeventh_val[ctr_idx] |= MHPMEVENTH_BIT_OF;
-                riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
+                riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
             }
         } else {
             counter->mhpmcounterh_val++;
@@ -172,7 +172,7 @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx)
         /* Generate interrupt only if OF bit is clear */
         if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) {
             env->mhpmevent_val[ctr_idx] |= MHPMEVENT_BIT_OF;
-            riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
+            riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
         }
     } else {
         counter->mhpmcounter_val++;
@@ -371,7 +371,7 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu,
         /* Generate interrupt only if OF bit is clear */
         if (!(*mhpmevent_val & of_bit_mask)) {
             *mhpmevent_val |= of_bit_mask;
-            riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
+            riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
         }
     }
 }
diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
index b654f91af9..8d245bed3a 100644
--- a/target/riscv/time_helper.c
+++ b/target/riscv/time_helper.c
@@ -27,25 +27,24 @@ static void riscv_vstimer_cb(void *opaque)
     RISCVCPU *cpu = opaque;
     CPURISCVState *env = &cpu->env;
     env->vstime_irq = 1;
-    riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
+    riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1));
 }
 
 static void riscv_stimer_cb(void *opaque)
 {
     RISCVCPU *cpu = opaque;
-    riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
+    riscv_cpu_update_mip(&cpu->env, MIP_STIP, BOOL_TO_MASK(1));
 }
 
 /*
  * Called when timecmp is written to update the QEMU timer or immediately
  * trigger timer interrupt if mtimecmp <= current timer value.
  */
-void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
+void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
                                uint64_t timecmp, uint64_t delta,
                                uint32_t timer_irq)
 {
     uint64_t diff, ns_diff, next;
-    CPURISCVState *env = &cpu->env;
     RISCVAclintMTimerState *mtimer = env->rdtime_fn_arg;
     uint32_t timebase_freq = mtimer->timebase_freq;
     uint64_t rtc_r = env->rdtime_fn(env->rdtime_fn_arg) + delta;
@@ -57,9 +56,9 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
          */
         if (timer_irq == MIP_VSTIP) {
             env->vstime_irq = 1;
-            riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
+            riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1));
         } else {
-            riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
+            riscv_cpu_update_mip(env, MIP_STIP, BOOL_TO_MASK(1));
         }
         return;
     }
@@ -67,9 +66,9 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
     /* Clear the [VS|S]TIP bit in mip */
     if (timer_irq == MIP_VSTIP) {
         env->vstime_irq = 0;
-        riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0));
+        riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0));
     } else {
-        riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
+        riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0));
     }
 
     /*
diff --git a/target/riscv/time_helper.h b/target/riscv/time_helper.h
index 7b3cdcc350..cacd79b80c 100644
--- a/target/riscv/time_helper.h
+++ b/target/riscv/time_helper.h
@@ -22,7 +22,7 @@
 #include "cpu.h"
 #include "qemu/timer.h"
 
-void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
+void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
                                uint64_t timecmp, uint64_t delta,
                                uint32_t timer_irq);
 void riscv_timer_init(RISCVCPU *cpu);
-- 
2.25.1

Re: [PATCH 3/4] target/riscv: Simplify type conversion for CPURISCVState

[Daniel Henrique Barboza]

On 3/9/23 04:13, Weiwei Li wrote:
> Use CPURISCVState as argument directly in riscv_cpu_update_mip and
> riscv_timer_write_timecmp, since type converts from CPURISCVState to
> RISCVCPU in many caller of them and then back to CPURISCVState in them.
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu.c         |  6 +++---
>   target/riscv/cpu.h         |  3 ++-
>   target/riscv/cpu_helper.c  |  8 ++++----
>   target/riscv/csr.c         | 35 +++++++++++------------------------
>   target/riscv/pmu.c         |  6 +++---
>   target/riscv/time_helper.c | 15 +++++++--------
>   target/riscv/time_helper.h |  2 +-
>   7 files changed, 31 insertions(+), 44 deletions(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1e97473af2..16e465a0ab 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1302,7 +1302,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
>               if (kvm_enabled()) {
>                   kvm_riscv_set_irq(cpu, irq, level);
>               } else {
> -                riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
> +                riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level));
>               }
>                break;
>           case IRQ_S_EXT:
> @@ -1310,7 +1310,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
>                   kvm_riscv_set_irq(cpu, irq, level);
>               } else {
>                   env->external_seip = level;
> -                riscv_cpu_update_mip(cpu, 1 << irq,
> +                riscv_cpu_update_mip(env, 1 << irq,
>                                        BOOL_TO_MASK(level | env->software_seip));
>               }
>               break;
> @@ -1336,7 +1336,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
>           }
>   
>           /* Update mip.SGEIP bit */
> -        riscv_cpu_update_mip(cpu, MIP_SGEIP,
> +        riscv_cpu_update_mip(env, MIP_SGEIP,
>                                BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
>       } else {
>           g_assert_not_reached();
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 638e47c75a..5adefe4ab5 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -602,7 +602,8 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
>   bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
>   void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
>   int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
> -uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
> +uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
> +                              uint64_t value);
>   #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
>   void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
>                                void *arg);
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index e677255f87..824f0cbd92 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -590,7 +590,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
>            *
>            * To solve this, we check and inject interrupt after setting V=1.
>            */
> -        riscv_cpu_update_mip(env_archcpu(env), 0, 0);
> +        riscv_cpu_update_mip(env, 0, 0);
>       }
>   }
>   
> @@ -610,10 +610,10 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
>       }
>   }
>   
> -uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
> +uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
> +                              uint64_t value)
>   {
> -    CPURISCVState *env = &cpu->env;
> -    CPUState *cs = CPU(cpu);
> +    CPUState *cs = env_cpu(env);
>       uint64_t gein, vsgein = 0, vstip = 0, old = env->mip;
>   
>       if (riscv_cpu_virt_enabled(env)) {
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index b453d8e8ca..53143f4d9a 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -990,15 +990,13 @@ static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
>   static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
>                                         target_ulong val)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
>       if (riscv_cpu_mxl(env) == MXL_RV32) {
>           env->vstimecmp = deposit64(env->vstimecmp, 0, 32, (uint64_t)val);
>       } else {
>           env->vstimecmp = val;
>       }
>   
> -    riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
> +    riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
>                                 env->htimedelta, MIP_VSTIP);
>   
>       return RISCV_EXCP_NONE;
> @@ -1007,10 +1005,8 @@ static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
>   static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
>                                          target_ulong val)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
>       env->vstimecmp = deposit64(env->vstimecmp, 32, 32, (uint64_t)val);
> -    riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
> +    riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
>                                 env->htimedelta, MIP_VSTIP);
>   
>       return RISCV_EXCP_NONE;
> @@ -1043,8 +1039,6 @@ static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
>   static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
>                                        target_ulong val)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
>       if (riscv_cpu_virt_enabled(env)) {
>           if (env->hvictl & HVICTL_VTI) {
>               return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> @@ -1058,7 +1052,7 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
>           env->stimecmp = val;
>       }
>   
> -    riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP);
> +    riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
>   
>       return RISCV_EXCP_NONE;
>   }
> @@ -1066,8 +1060,6 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
>   static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
>                                         target_ulong val)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
>       if (riscv_cpu_virt_enabled(env)) {
>           if (env->hvictl & HVICTL_VTI) {
>               return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> @@ -1076,7 +1068,7 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
>       }
>   
>       env->stimecmp = deposit64(env->stimecmp, 32, 32, (uint64_t)val);
> -    riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP);
> +    riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
>   
>       return RISCV_EXCP_NONE;
>   }
> @@ -2211,7 +2203,6 @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
>                                   uint64_t *ret_val,
>                                   uint64_t new_val, uint64_t wr_mask)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
>       uint64_t old_mip, mask = wr_mask & delegable_ints;
>       uint32_t gin;
>   
> @@ -2220,14 +2211,14 @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
>           new_val |= env->external_seip * MIP_SEIP;
>       }
>   
> -    if (cpu->cfg.ext_sstc && (env->priv == PRV_M) &&
> +    if (riscv_cpu_cfg(env)->ext_sstc && (env->priv == PRV_M) &&
>           get_field(env->menvcfg, MENVCFG_STCE)) {
>           /* sstc extension forbids STIP & VSTIP to be writeable in mip */
>           mask = mask & ~(MIP_STIP | MIP_VSTIP);
>       }
>   
>       if (mask) {
> -        old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask));
> +        old_mip = riscv_cpu_update_mip(env, mask, (new_val & mask));
>       } else {
>           old_mip = env->mip;
>       }
> @@ -2987,7 +2978,7 @@ static RISCVException write_hgeie(CPURISCVState *env, int csrno,
>       val &= ((((target_ulong)1) << env->geilen) - 1) << 1;
>       env->hgeie = val;
>       /* Update mip.SGEIP bit */
> -    riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP,
> +    riscv_cpu_update_mip(env, MIP_SGEIP,
>                            BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
>       return RISCV_EXCP_NONE;
>   }
> @@ -3056,8 +3047,6 @@ static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
>   static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
>                                          target_ulong val)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
>       if (!env->rdtime_fn) {
>           return RISCV_EXCP_ILLEGAL_INST;
>       }
> @@ -3068,8 +3057,8 @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
>           env->htimedelta = val;
>       }
>   
> -    if (cpu->cfg.ext_sstc && env->rdtime_fn) {
> -        riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
> +    if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) {
> +        riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
>                                     env->htimedelta, MIP_VSTIP);
>       }
>   
> @@ -3090,16 +3079,14 @@ static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
>   static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
>                                           target_ulong val)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
>       if (!env->rdtime_fn) {
>           return RISCV_EXCP_ILLEGAL_INST;
>       }
>   
>       env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
>   
> -    if (cpu->cfg.ext_sstc && env->rdtime_fn) {
> -        riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
> +    if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) {
> +        riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
>                                     env->htimedelta, MIP_VSTIP);
>       }
>   
> diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
> index a200741083..22e2283c76 100644
> --- a/target/riscv/pmu.c
> +++ b/target/riscv/pmu.c
> @@ -133,7 +133,7 @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx)
>               /* Generate interrupt only if OF bit is clear */
>               if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) {
>                   env->mhpmeventh_val[ctr_idx] |= MHPMEVENTH_BIT_OF;
> -                riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
> +                riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
>               }
>           } else {
>               counter->mhpmcounterh_val++;
> @@ -172,7 +172,7 @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx)
>           /* Generate interrupt only if OF bit is clear */
>           if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) {
>               env->mhpmevent_val[ctr_idx] |= MHPMEVENT_BIT_OF;
> -            riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
> +            riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
>           }
>       } else {
>           counter->mhpmcounter_val++;
> @@ -371,7 +371,7 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu,
>           /* Generate interrupt only if OF bit is clear */
>           if (!(*mhpmevent_val & of_bit_mask)) {
>               *mhpmevent_val |= of_bit_mask;
> -            riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
> +            riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
>           }
>       }
>   }
> diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
> index b654f91af9..8d245bed3a 100644
> --- a/target/riscv/time_helper.c
> +++ b/target/riscv/time_helper.c
> @@ -27,25 +27,24 @@ static void riscv_vstimer_cb(void *opaque)
>       RISCVCPU *cpu = opaque;
>       CPURISCVState *env = &cpu->env;
>       env->vstime_irq = 1;
> -    riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
> +    riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1));
>   }
>   
>   static void riscv_stimer_cb(void *opaque)
>   {
>       RISCVCPU *cpu = opaque;
> -    riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
> +    riscv_cpu_update_mip(&cpu->env, MIP_STIP, BOOL_TO_MASK(1));
>   }
>   
>   /*
>    * Called when timecmp is written to update the QEMU timer or immediately
>    * trigger timer interrupt if mtimecmp <= current timer value.
>    */
> -void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
> +void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
>                                  uint64_t timecmp, uint64_t delta,
>                                  uint32_t timer_irq)
>   {
>       uint64_t diff, ns_diff, next;
> -    CPURISCVState *env = &cpu->env;
>       RISCVAclintMTimerState *mtimer = env->rdtime_fn_arg;
>       uint32_t timebase_freq = mtimer->timebase_freq;
>       uint64_t rtc_r = env->rdtime_fn(env->rdtime_fn_arg) + delta;
> @@ -57,9 +56,9 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
>            */
>           if (timer_irq == MIP_VSTIP) {
>               env->vstime_irq = 1;
> -            riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
> +            riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1));
>           } else {
> -            riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
> +            riscv_cpu_update_mip(env, MIP_STIP, BOOL_TO_MASK(1));
>           }
>           return;
>       }
> @@ -67,9 +66,9 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
>       /* Clear the [VS|S]TIP bit in mip */
>       if (timer_irq == MIP_VSTIP) {
>           env->vstime_irq = 0;
> -        riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0));
> +        riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0));
>       } else {
> -        riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
> +        riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0));
>       }
>   
>       /*
> diff --git a/target/riscv/time_helper.h b/target/riscv/time_helper.h
> index 7b3cdcc350..cacd79b80c 100644
> --- a/target/riscv/time_helper.h
> +++ b/target/riscv/time_helper.h
> @@ -22,7 +22,7 @@
>   #include "cpu.h"
>   #include "qemu/timer.h"
>   
> -void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
> +void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
>                                  uint64_t timecmp, uint64_t delta,
>                                  uint32_t timer_irq);
>   void riscv_timer_init(RISCVCPU *cpu);

Re: [PATCH 3/4] target/riscv: Simplify type conversion for CPURISCVState

[Alistair Francis]

On Thu, Mar 9, 2023 at 5:14 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Use CPURISCVState as argument directly in riscv_cpu_update_mip and
> riscv_timer_write_timecmp, since type converts from CPURISCVState to
> RISCVCPU in many caller of them and then back to CPURISCVState in them.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c         |  6 +++---
>  target/riscv/cpu.h         |  3 ++-
>  target/riscv/cpu_helper.c  |  8 ++++----
>  target/riscv/csr.c         | 35 +++++++++++------------------------
>  target/riscv/pmu.c         |  6 +++---
>  target/riscv/time_helper.c | 15 +++++++--------
>  target/riscv/time_helper.h |  2 +-
>  7 files changed, 31 insertions(+), 44 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1e97473af2..16e465a0ab 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1302,7 +1302,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
>              if (kvm_enabled()) {
>                  kvm_riscv_set_irq(cpu, irq, level);
>              } else {
> -                riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
> +                riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level));
>              }
>               break;
>          case IRQ_S_EXT:
> @@ -1310,7 +1310,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
>                  kvm_riscv_set_irq(cpu, irq, level);
>              } else {
>                  env->external_seip = level;
> -                riscv_cpu_update_mip(cpu, 1 << irq,
> +                riscv_cpu_update_mip(env, 1 << irq,
>                                       BOOL_TO_MASK(level | env->software_seip));
>              }
>              break;
> @@ -1336,7 +1336,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
>          }
>
>          /* Update mip.SGEIP bit */
> -        riscv_cpu_update_mip(cpu, MIP_SGEIP,
> +        riscv_cpu_update_mip(env, MIP_SGEIP,
>                               BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
>      } else {
>          g_assert_not_reached();
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 638e47c75a..5adefe4ab5 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -602,7 +602,8 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
>  bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
>  void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
>  int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
> -uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
> +uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
> +                              uint64_t value);
>  #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
>  void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
>                               void *arg);
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index e677255f87..824f0cbd92 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -590,7 +590,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
>           *
>           * To solve this, we check and inject interrupt after setting V=1.
>           */
> -        riscv_cpu_update_mip(env_archcpu(env), 0, 0);
> +        riscv_cpu_update_mip(env, 0, 0);
>      }
>  }
>
> @@ -610,10 +610,10 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts)
>      }
>  }
>
> -uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
> +uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask,
> +                              uint64_t value)
>  {
> -    CPURISCVState *env = &cpu->env;
> -    CPUState *cs = CPU(cpu);
> +    CPUState *cs = env_cpu(env);
>      uint64_t gein, vsgein = 0, vstip = 0, old = env->mip;
>
>      if (riscv_cpu_virt_enabled(env)) {
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index b453d8e8ca..53143f4d9a 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -990,15 +990,13 @@ static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
>  static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
>                                        target_ulong val)
>  {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
>      if (riscv_cpu_mxl(env) == MXL_RV32) {
>          env->vstimecmp = deposit64(env->vstimecmp, 0, 32, (uint64_t)val);
>      } else {
>          env->vstimecmp = val;
>      }
>
> -    riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
> +    riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
>                                env->htimedelta, MIP_VSTIP);
>
>      return RISCV_EXCP_NONE;
> @@ -1007,10 +1005,8 @@ static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
>  static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
>                                         target_ulong val)
>  {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
>      env->vstimecmp = deposit64(env->vstimecmp, 32, 32, (uint64_t)val);
> -    riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
> +    riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
>                                env->htimedelta, MIP_VSTIP);
>
>      return RISCV_EXCP_NONE;
> @@ -1043,8 +1039,6 @@ static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
>  static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
>                                       target_ulong val)
>  {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
>      if (riscv_cpu_virt_enabled(env)) {
>          if (env->hvictl & HVICTL_VTI) {
>              return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> @@ -1058,7 +1052,7 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
>          env->stimecmp = val;
>      }
>
> -    riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP);
> +    riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
>
>      return RISCV_EXCP_NONE;
>  }
> @@ -1066,8 +1060,6 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
>  static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
>                                        target_ulong val)
>  {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
>      if (riscv_cpu_virt_enabled(env)) {
>          if (env->hvictl & HVICTL_VTI) {
>              return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> @@ -1076,7 +1068,7 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
>      }
>
>      env->stimecmp = deposit64(env->stimecmp, 32, 32, (uint64_t)val);
> -    riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP);
> +    riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
>
>      return RISCV_EXCP_NONE;
>  }
> @@ -2211,7 +2203,6 @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
>                                  uint64_t *ret_val,
>                                  uint64_t new_val, uint64_t wr_mask)
>  {
> -    RISCVCPU *cpu = env_archcpu(env);
>      uint64_t old_mip, mask = wr_mask & delegable_ints;
>      uint32_t gin;
>
> @@ -2220,14 +2211,14 @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
>          new_val |= env->external_seip * MIP_SEIP;
>      }
>
> -    if (cpu->cfg.ext_sstc && (env->priv == PRV_M) &&
> +    if (riscv_cpu_cfg(env)->ext_sstc && (env->priv == PRV_M) &&
>          get_field(env->menvcfg, MENVCFG_STCE)) {
>          /* sstc extension forbids STIP & VSTIP to be writeable in mip */
>          mask = mask & ~(MIP_STIP | MIP_VSTIP);
>      }
>
>      if (mask) {
> -        old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask));
> +        old_mip = riscv_cpu_update_mip(env, mask, (new_val & mask));
>      } else {
>          old_mip = env->mip;
>      }
> @@ -2987,7 +2978,7 @@ static RISCVException write_hgeie(CPURISCVState *env, int csrno,
>      val &= ((((target_ulong)1) << env->geilen) - 1) << 1;
>      env->hgeie = val;
>      /* Update mip.SGEIP bit */
> -    riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP,
> +    riscv_cpu_update_mip(env, MIP_SGEIP,
>                           BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
>      return RISCV_EXCP_NONE;
>  }
> @@ -3056,8 +3047,6 @@ static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
>  static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
>                                         target_ulong val)
>  {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
>      if (!env->rdtime_fn) {
>          return RISCV_EXCP_ILLEGAL_INST;
>      }
> @@ -3068,8 +3057,8 @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
>          env->htimedelta = val;
>      }
>
> -    if (cpu->cfg.ext_sstc && env->rdtime_fn) {
> -        riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
> +    if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) {
> +        riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
>                                    env->htimedelta, MIP_VSTIP);
>      }
>
> @@ -3090,16 +3079,14 @@ static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
>  static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
>                                          target_ulong val)
>  {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
>      if (!env->rdtime_fn) {
>          return RISCV_EXCP_ILLEGAL_INST;
>      }
>
>      env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
>
> -    if (cpu->cfg.ext_sstc && env->rdtime_fn) {
> -        riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
> +    if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) {
> +        riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
>                                    env->htimedelta, MIP_VSTIP);
>      }
>
> diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
> index a200741083..22e2283c76 100644
> --- a/target/riscv/pmu.c
> +++ b/target/riscv/pmu.c
> @@ -133,7 +133,7 @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx)
>              /* Generate interrupt only if OF bit is clear */
>              if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) {
>                  env->mhpmeventh_val[ctr_idx] |= MHPMEVENTH_BIT_OF;
> -                riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
> +                riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
>              }
>          } else {
>              counter->mhpmcounterh_val++;
> @@ -172,7 +172,7 @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx)
>          /* Generate interrupt only if OF bit is clear */
>          if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) {
>              env->mhpmevent_val[ctr_idx] |= MHPMEVENT_BIT_OF;
> -            riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
> +            riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
>          }
>      } else {
>          counter->mhpmcounter_val++;
> @@ -371,7 +371,7 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu,
>          /* Generate interrupt only if OF bit is clear */
>          if (!(*mhpmevent_val & of_bit_mask)) {
>              *mhpmevent_val |= of_bit_mask;
> -            riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1));
> +            riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
>          }
>      }
>  }
> diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
> index b654f91af9..8d245bed3a 100644
> --- a/target/riscv/time_helper.c
> +++ b/target/riscv/time_helper.c
> @@ -27,25 +27,24 @@ static void riscv_vstimer_cb(void *opaque)
>      RISCVCPU *cpu = opaque;
>      CPURISCVState *env = &cpu->env;
>      env->vstime_irq = 1;
> -    riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
> +    riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1));
>  }
>
>  static void riscv_stimer_cb(void *opaque)
>  {
>      RISCVCPU *cpu = opaque;
> -    riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
> +    riscv_cpu_update_mip(&cpu->env, MIP_STIP, BOOL_TO_MASK(1));
>  }
>
>  /*
>   * Called when timecmp is written to update the QEMU timer or immediately
>   * trigger timer interrupt if mtimecmp <= current timer value.
>   */
> -void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
> +void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
>                                 uint64_t timecmp, uint64_t delta,
>                                 uint32_t timer_irq)
>  {
>      uint64_t diff, ns_diff, next;
> -    CPURISCVState *env = &cpu->env;
>      RISCVAclintMTimerState *mtimer = env->rdtime_fn_arg;
>      uint32_t timebase_freq = mtimer->timebase_freq;
>      uint64_t rtc_r = env->rdtime_fn(env->rdtime_fn_arg) + delta;
> @@ -57,9 +56,9 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
>           */
>          if (timer_irq == MIP_VSTIP) {
>              env->vstime_irq = 1;
> -            riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
> +            riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1));
>          } else {
> -            riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
> +            riscv_cpu_update_mip(env, MIP_STIP, BOOL_TO_MASK(1));
>          }
>          return;
>      }
> @@ -67,9 +66,9 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
>      /* Clear the [VS|S]TIP bit in mip */
>      if (timer_irq == MIP_VSTIP) {
>          env->vstime_irq = 0;
> -        riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0));
> +        riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0));
>      } else {
> -        riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
> +        riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0));
>      }
>
>      /*
> diff --git a/target/riscv/time_helper.h b/target/riscv/time_helper.h
> index 7b3cdcc350..cacd79b80c 100644
> --- a/target/riscv/time_helper.h
> +++ b/target/riscv/time_helper.h
> @@ -22,7 +22,7 @@
>  #include "cpu.h"
>  #include "qemu/timer.h"
>
> -void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
> +void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
>                                 uint64_t timecmp, uint64_t delta,
>                                 uint32_t timer_irq);
>  void riscv_timer_init(RISCVCPU *cpu);
> --
> 2.25.1
>
>

[PATCH 4/4] target/riscv: Simplify arguments for riscv_csrrw_check

[Weiwei Li]

Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
directly.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/csr.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 53143f4d9a..80fc15e4d6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3755,15 +3755,14 @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 
 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
                                                int csrno,
-                                               bool write_mask,
-                                               RISCVCPU *cpu)
+                                               bool write_mask)
 {
     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
     bool read_only = get_field(csrno, 0xC00) == 3;
     int csr_min_priv = csr_ops[csrno].min_priv_ver;
 
     /* ensure the CSR extension is enabled */
-    if (!cpu->cfg.ext_icsr) {
+    if (!riscv_cpu_cfg(env)->ext_icsr) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -3859,9 +3858,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
-    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
+    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
@@ -3914,9 +3911,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 new_value, Int128 write_mask)
 {
     RISCVException ret;
-    RISCVCPU *cpu = env_archcpu(env);
 
-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
+    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
-- 
2.25.1

Re: [PATCH 4/4] target/riscv: Simplify arguments for riscv_csrrw_check

[Daniel Henrique Barboza]

On 3/9/23 04:13, Weiwei Li wrote:
> Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
> directly.
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/csr.c | 12 ++++--------
>   1 file changed, 4 insertions(+), 8 deletions(-)
> 
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 53143f4d9a..80fc15e4d6 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3755,15 +3755,14 @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
>   
>   static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
>                                                  int csrno,
> -                                               bool write_mask,
> -                                               RISCVCPU *cpu)
> +                                               bool write_mask)
>   {
>       /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
>       bool read_only = get_field(csrno, 0xC00) == 3;
>       int csr_min_priv = csr_ops[csrno].min_priv_ver;
>   
>       /* ensure the CSR extension is enabled */
> -    if (!cpu->cfg.ext_icsr) {
> +    if (!riscv_cpu_cfg(env)->ext_icsr) {
>           return RISCV_EXCP_ILLEGAL_INST;
>       }
>   
> @@ -3859,9 +3858,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
>                              target_ulong *ret_value,
>                              target_ulong new_value, target_ulong write_mask)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
> +    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
>       if (ret != RISCV_EXCP_NONE) {
>           return ret;
>       }
> @@ -3914,9 +3911,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
>                                   Int128 new_value, Int128 write_mask)
>   {
>       RISCVException ret;
> -    RISCVCPU *cpu = env_archcpu(env);
>   
> -    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
> +    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
>       if (ret != RISCV_EXCP_NONE) {
>           return ret;
>       }

Re: [PATCH 4/4] target/riscv: Simplify arguments for riscv_csrrw_check

[Alistair Francis]

On Thu, Mar 9, 2023 at 5:14 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
> directly.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 12 ++++--------
>  1 file changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 53143f4d9a..80fc15e4d6 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3755,15 +3755,14 @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
>
>  static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
>                                                 int csrno,
> -                                               bool write_mask,
> -                                               RISCVCPU *cpu)
> +                                               bool write_mask)
>  {
>      /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
>      bool read_only = get_field(csrno, 0xC00) == 3;
>      int csr_min_priv = csr_ops[csrno].min_priv_ver;
>
>      /* ensure the CSR extension is enabled */
> -    if (!cpu->cfg.ext_icsr) {
> +    if (!riscv_cpu_cfg(env)->ext_icsr) {
>          return RISCV_EXCP_ILLEGAL_INST;
>      }
>
> @@ -3859,9 +3858,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
>                             target_ulong *ret_value,
>                             target_ulong new_value, target_ulong write_mask)
>  {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
> +    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
>      if (ret != RISCV_EXCP_NONE) {
>          return ret;
>      }
> @@ -3914,9 +3911,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
>                                  Int128 new_value, Int128 write_mask)
>  {
>      RISCVException ret;
> -    RISCVCPU *cpu = env_archcpu(env);
>
> -    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
> +    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
>      if (ret != RISCV_EXCP_NONE) {
>          return ret;
>      }
> --
> 2.25.1
>
>

Re: [PATCH 4/4] target/riscv: Simplify arguments for riscv_csrrw_check

[Philippe Mathieu-Daudé]

On 9/3/23 08:13, Weiwei Li wrote:
> Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
> directly.
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/csr.c | 12 ++++--------
>   1 file changed, 4 insertions(+), 8 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Re: [PATCH 0/4] target/riscv: Some CPURISCVState related cleanup and simplification

[Alistair Francis]

On Thu, Mar 9, 2023 at 5:15 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> The patchset tries to:
>
> - Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.
> - Use env_archcpu() to get RISCVCPU pointer from env directly
> - Use CPURISCVState as argument directly in riscv_cpu_update_mip and riscv_timer_write_timecmp to simplify type conversion
> - Remove RISCVCPU argument of riscv_csrrw_check, and get cfg infomation from CPURISCVState directly
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-cleanup-upstream
>
> Weiwei Li (4):
>   target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
>   target/riscv: Simplify getting RISCVCPU pointer from env
>   target/riscv: Simplify type conversion for CPURISCVState
>   target/riscv: Simplify arguments for riscv_csrrw_check

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c         |  6 +--
>  target/riscv/cpu.h         |  3 +-
>  target/riscv/cpu_helper.c  | 17 ++++----
>  target/riscv/csr.c         | 87 ++++++++++++--------------------------
>  target/riscv/gdbstub.c     |  4 +-
>  target/riscv/pmu.c         | 14 +++---
>  target/riscv/time_helper.c | 15 +++----
>  target/riscv/time_helper.h |  2 +-
>  8 files changed, 57 insertions(+), 91 deletions(-)
>
> --
> 2.25.1
>
>