From: Alistair Francis <alistair23@gmail.com>
To: Frank Chang <frank.chang@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: Re: [PATCH v6 17/72] target/riscv: rvv-1.0: configure instructions
Date: Tue, 19 Jan 2021 10:59:56 -0800 [thread overview]
Message-ID: <CAKmqyKMFgh0NQQgmrV9-+AMyCmABXY4JOfb90RzkDXpEipO3GA@mail.gmail.com> (raw)
In-Reply-To: <20210112093950.17530-18-frank.chang@sifive.com>
On Tue, Jan 12, 2021 at 2:06 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 53 +++++++++----------------
> target/riscv/vector_helper.c | 14 ++++++-
> 2 files changed, 31 insertions(+), 36 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index ccfa93cf2f8..a3732e76e09 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -132,28 +132,29 @@ static bool require_noover_seg(const int8_t dst, const int8_t nf,
> return !is_overlapped(dst, nf, src, 1);
> }
>
> -static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
> +static bool do_vsetvl(DisasContext *ctx, int rd, int rs1, TCGv s2)
> {
> - TCGv s1, s2, dst;
> + TCGv s1, dst;
>
> if (!require_rvv(ctx) || !has_ext(ctx, RVV)) {
> return false;
> }
>
> - s2 = tcg_temp_new();
> dst = tcg_temp_new();
>
> - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
> - if (a->rs1 == 0) {
> + if (rd == 0 && rs1 == 0) {
> + s1 = tcg_temp_new();
> + tcg_gen_mov_tl(s1, cpu_vl);
> + } else if (rs1 == 0) {
> /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
> s1 = tcg_const_tl(RV_VLEN_MAX);
> } else {
> s1 = tcg_temp_new();
> - gen_get_gpr(s1, a->rs1);
> + gen_get_gpr(s1, rs1);
> }
> - gen_get_gpr(s2, a->rs2);
> +
> gen_helper_vsetvl(dst, cpu_env, s1, s2);
> - gen_set_gpr(a->rd, dst);
> + gen_set_gpr(rd, dst);
> mark_vs_dirty(ctx);
> tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
> lookup_and_goto_ptr(ctx);
> @@ -165,35 +166,17 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
> return true;
> }
>
> -static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
> +static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
> {
> - TCGv s1, s2, dst;
> -
> - if (!require_rvv(ctx) || !has_ext(ctx, RVV)) {
> - return false;
> - }
> -
> - s2 = tcg_const_tl(a->zimm);
> - dst = tcg_temp_new();
> -
> - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
> - if (a->rs1 == 0) {
> - /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
> - s1 = tcg_const_tl(RV_VLEN_MAX);
> - } else {
> - s1 = tcg_temp_new();
> - gen_get_gpr(s1, a->rs1);
> - }
> - gen_helper_vsetvl(dst, cpu_env, s1, s2);
> - gen_set_gpr(a->rd, dst);
> - mark_vs_dirty(ctx);
> - gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
> - ctx->base.is_jmp = DISAS_NORETURN;
> + TCGv s2 = tcg_temp_new();
> + gen_get_gpr(s2, a->rs2);
> + return do_vsetvl(ctx, a->rd, a->rs1, s2);
> +}
>
> - tcg_temp_free(s1);
> - tcg_temp_free(s2);
> - tcg_temp_free(dst);
> - return true;
> +static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
> +{
> + TCGv s2 = tcg_const_tl(a->zimm);
> + return do_vsetvl(ctx, a->rd, a->rs1, s2);
> }
>
> /* vector register offset from env */
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 89aa7cbf73f..61917d34ffe 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -31,12 +31,24 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> {
> int vlmax, vl;
> RISCVCPU *cpu = env_archcpu(env);
> + uint64_t lmul = FIELD_EX64(s2, VTYPE, VLMUL);
> uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
> uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
> bool vill = FIELD_EX64(s2, VTYPE, VILL);
> target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
>
> - if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
> + if (lmul & 4) {
> + /* Fractional LMUL. */
> + if (lmul == 4 ||
> + cpu->cfg.elen >> (8 - lmul) < sew) {
> + vill = true;
> + }
> + }
> +
> + if ((sew > cpu->cfg.elen)
> + || vill
> + || (ediv != 0)
> + || (reserved != 0)) {
> /* only set vill bit. */
> env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
> env->vl = 0;
> --
> 2.17.1
>
>
next prev parent reply other threads:[~2021-01-19 19:38 UTC|newest]
Thread overview: 107+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-12 9:38 [PATCH v6 00/72] support vector extension v1.0 frank.chang
2021-01-12 9:38 ` [PATCH v6 01/72] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
2021-01-12 9:38 ` [PATCH v6 02/72] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2021-01-19 16:34 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 03/72] target/riscv: rvv-1.0: add mstatus VS field frank.chang
2021-01-19 16:36 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 04/72] target/riscv: rvv-1.0: add sstatus " frank.chang
2021-01-19 16:36 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 05/72] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
2021-01-19 16:37 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 06/72] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
2021-01-19 18:47 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 07/72] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang
2021-01-19 16:47 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 08/72] target/riscv: rvv-1.0: add vcsr register frank.chang
2021-01-19 17:38 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 09/72] target/riscv: rvv-1.0: add vlenb register frank.chang
2021-01-19 17:39 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 10/72] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
2021-01-19 17:40 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 11/72] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
2021-01-19 17:41 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 12/72] target/riscv: rvv-1.0: add fractional LMUL frank.chang
2021-01-19 18:43 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 13/72] target/riscv: rvv-1.0: add VMA and VTA frank.chang
2021-01-19 18:51 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 14/72] target/riscv: rvv-1.0: update check functions frank.chang
2021-01-28 21:15 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 15/72] target/riscv: introduce more imm value modes in translator functions frank.chang
2021-01-19 18:55 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 16/72] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
2021-01-19 18:58 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 17/72] target/riscv: rvv-1.0: configure instructions frank.chang
2021-01-19 18:59 ` Alistair Francis [this message]
2021-01-12 9:38 ` [PATCH v6 18/72] target/riscv: rvv-1.0: stride load and store instructions frank.chang
2021-01-19 19:03 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 19/72] target/riscv: rvv-1.0: index " frank.chang
2021-01-19 19:09 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 20/72] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2021-01-19 19:22 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 21/72] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2021-01-19 19:19 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 22/72] target/riscv: rvv-1.0: amo operations frank.chang
2021-01-25 23:19 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 23/72] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
2021-01-25 23:24 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 24/72] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
2021-01-25 23:33 ` Alistair Francis
2021-01-12 9:38 ` [PATCH v6 25/72] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
2021-01-25 23:42 ` Alistair Francis
2021-01-12 9:39 ` [PATCH v6 26/72] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
2021-01-25 23:49 ` Alistair Francis
2021-01-12 9:39 ` [PATCH v6 27/72] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
2021-01-25 23:50 ` Alistair Francis
2021-01-12 9:39 ` [PATCH v6 28/72] target/riscv: rvv-1.0: mask population count instruction frank.chang
2021-01-12 9:39 ` [PATCH v6 29/72] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
2021-01-12 9:39 ` [PATCH v6 30/72] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 31/72] target/riscv: rvv-1.0: iota instruction frank.chang
2021-01-12 9:39 ` [PATCH v6 32/72] target/riscv: rvv-1.0: element index instruction frank.chang
2021-01-12 9:39 ` [PATCH v6 33/72] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
2021-01-12 9:39 ` [PATCH v6 34/72] target/riscv: rvv-1.0: register gather instructions frank.chang
2021-01-28 21:18 ` Alistair Francis
2021-01-12 9:39 ` [PATCH v6 35/72] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 36/72] target/riscv: rvv-1.0: floating-point move instruction frank.chang
2021-01-28 21:20 ` Alistair Francis
2021-01-12 9:39 ` [PATCH v6 37/72] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 38/72] target/riscv: rvv-1.0: whole register " frank.chang
2021-01-12 9:39 ` [PATCH v6 39/72] target/riscv: rvv-1.0: integer extension instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 40/72] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 41/72] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 42/72] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
2021-01-12 9:39 ` [PATCH v6 43/72] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 44/72] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 45/72] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 46/72] target/riscv: rvv-1.0: integer comparison instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 47/72] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 48/72] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 49/72] target/riscv: rvv-1.0: slide instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 50/72] target/riscv: rvv-1.0: floating-point " frank.chang
2021-01-12 9:39 ` [PATCH v6 51/72] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 52/72] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
2021-01-12 9:39 ` [PATCH v6 53/72] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 54/72] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 55/72] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
2021-01-12 9:39 ` [PATCH v6 56/72] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang
2021-01-12 9:39 ` [PATCH v6 57/72] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
2021-01-12 9:39 ` [PATCH v6 58/72] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 59/72] target/riscv: introduce floating-point rounding mode enum frank.chang
2021-01-12 9:39 ` [PATCH v6 60/72] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
2021-01-12 9:39 ` [PATCH v6 61/72] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
2021-01-12 9:39 ` [PATCH v6 62/72] target/riscv: add "set round to odd" rounding mode helper function frank.chang
2021-01-12 9:39 ` [PATCH v6 63/72] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
2021-01-12 9:39 ` [PATCH v6 64/72] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang
2021-01-12 9:39 ` [PATCH v6 65/72] target/riscv: rvv-1.0: implement vstart CSR frank.chang
2021-01-12 9:39 ` [PATCH v6 66/72] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang
2021-01-12 9:39 ` [PATCH v6 67/72] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs frank.chang
2021-01-28 21:27 ` Alistair Francis
2021-01-12 9:39 ` [PATCH v6 68/72] target/riscv: gdb: modify gdb csr xml file to align with csr register map frank.chang
2021-01-25 23:53 ` Alistair Francis
2021-01-26 7:43 ` Frank Chang
2021-01-12 9:39 ` [PATCH v6 69/72] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang
2021-01-12 9:39 ` [PATCH v6 70/72] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang
2021-01-12 9:39 ` [PATCH v6 71/72] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang
2021-01-12 9:39 ` [PATCH v6 72/72] target/riscv: set mstatus.SD bit when writing fp CSRs frank.chang
2021-01-12 11:10 ` [PATCH v6 00/72] support vector extension v1.0 no-reply
2021-01-19 19:11 ` Alistair Francis
2021-01-26 6:14 ` Frank Chang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAKmqyKMFgh0NQQgmrV9-+AMyCmABXY4JOfb90RzkDXpEipO3GA@mail.gmail.com \
--to=alistair23@gmail.com \
--cc=Alistair.Francis@wdc.com \
--cc=frank.chang@sifive.com \
--cc=kbastian@mail.uni-paderborn.de \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=sagark@eecs.berkeley.edu \
--cc=zhiwei_liu@c-sky.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).