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Tue, 10 Jun 2025 04:37:00 -0700 (PDT) MIME-Version: 1.0 References: <20250602131226.1137281-1-djordje.todorovic@htecgroup.com> <20250602131226.1137281-5-djordje.todorovic@htecgroup.com> In-Reply-To: From: Alistair Francis Date: Tue, 10 Jun 2025 21:36:34 +1000 X-Gm-Features: AX0GCFvsPKwjHN0DerzzghDOBMs8twfBqYvQcq2dnYrHKmXvZWaXKi4gYr7tfgI Message-ID: Subject: Re: [PATCH v2 4/9] target/riscv: Add MIPS P8700 CSRs To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Djordje Todorovic , "qemu-devel@nongnu.org" , "qemu-riscv@nongnu.org" , "cfu@mips.com" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a35; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa35.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Jun 10, 2025 at 5:42=E2=80=AFPM Philippe Mathieu-Daud=C3=A9 wrote: > > On 2/6/25 15:12, Djordje Todorovic wrote: > > Define MIPS CSRs used for P8700 CPU. > > > > Signed-off-by: Chao-ying Fu > > Signed-off-by: Djordje Todorovic > > --- > > target/riscv/cpu.c | 3 + > > target/riscv/cpu.h | 7 ++ > > target/riscv/meson.build | 1 + > > target/riscv/mips_csr.c | 219 ++++++++++++++++++++++++++++++++++++++= + > > 4 files changed, 230 insertions(+) > > create mode 100644 target/riscv/mips_csr.c > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index c0e048a66d..984f93dd4a 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -497,6 +497,10 @@ struct CPUArchState { > > target_ulong rnmip; > > uint64_t rnmi_irqvec; > > uint64_t rnmi_excpvec; > > + > > + uint64_t mipstvec; /* MIPS tvec register */ > > + uint64_t mipsconfig[12]; /* MIPS config register */ > > + uint64_t mipspmacfg[15]; /* MIPS pmacfg register */ > > Pointless comments (not helpful at all). > > Alternatively: > > struct { > uint64_t tvec; > uint64_t config[12]; > uint64_t pmacfg[15]; > } mips; We don't want to store these in the CPUArchState. So you will need to create a vendor specific struct and you can then point to that from CPUArchState, similar to the existing `RISCVCSR *custom_csrs` Alistair > > > }; > >