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Thu, 27 Feb 2025 22:00:11 -0800 (PST) MIME-Version: 1.0 References: <20250122083617.3940240-1-ethan84@andestech.com> <20250122084630.3965707-1-ethan84@andestech.com> In-Reply-To: <20250122084630.3965707-1-ethan84@andestech.com> From: Alistair Francis Date: Fri, 28 Feb 2025 15:59:45 +1000 X-Gm-Features: AQ5f1JolcWETvuz44cANEudMwh4VzMX-TwnHa_LRGH2f30SZ6XS-9vo7OtkqCLA Message-ID: Subject: Re: [PATCH v10 5/8] hw/misc/riscv_iopmp_txn_info: Add struct for transaction infomation To: Ethan Chen Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, palmer@dabbelt.com, alistair.francis@wdc.com, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, peterx@redhat.com, david@redhat.com, philmd@linaro.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a2f; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Jan 22, 2025 at 6:49=E2=80=AFPM Ethan Chen via wrote: > > The entire valid transaction must fit within a single IOPMP entry. > However, during IOMMU translation, the transaction size is not > available. This structure defines the transaction information required > by the IOPMP. > > Signed-off-by: Ethan Chen > --- > include/hw/misc/riscv_iopmp_txn_info.h | 38 ++++++++++++++++++++++++++ > 1 file changed, 38 insertions(+) > create mode 100644 include/hw/misc/riscv_iopmp_txn_info.h > > diff --git a/include/hw/misc/riscv_iopmp_txn_info.h b/include/hw/misc/ris= cv_iopmp_txn_info.h > new file mode 100644 > index 0000000000..98bd26b68b > --- /dev/null > +++ b/include/hw/misc/riscv_iopmp_txn_info.h > @@ -0,0 +1,38 @@ > +/* > + * QEMU RISC-V IOPMP transaction information > + * > + * The transaction information structure provides the complete transacti= on > + * length to the IOPMP device > + * > + * Copyright (c) 2023-2025 Andes Tech. Corp. > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + * > + * This program is free software; you can redistribute it and/or modify = it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOU= T > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License= for > + * more details. > + * > + * You should have received a copy of the GNU General Public License alo= ng with > + * this program. If not, see . > + */ > + > +#ifndef RISCV_IOPMP_TXN_INFO_H > +#define RISCV_IOPMP_TXN_INFO_H > + > +typedef struct { > + /* The id of requestor */ > + uint32_t rrid:16; > + /* The start address of transaction */ > + uint64_t start_addr; > + /* The end address of transaction */ > + uint64_t end_addr; > + /* The stage of cascading IOPMP */ > + uint32_t stage; > +} riscv_iopmp_txn_info; Whoops, this should be CamelCase. Checkpatch should catch these type of errors, make sure you run it if you d= idn't Alistair > + > +#endif > -- > 2.34.1 > >