From: Alistair Francis <alistair23@gmail.com>
To: Frank Chang <frank.chang@sifive.com>
Cc: Chih-Min Chao <chihmin.chao@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>,
Alistair Francis <alistair.francis@opensource.wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PULL 16/18] target/riscv: change the api for RVF/RVD fmin/fmax
Date: Thu, 28 Oct 2021 21:30:57 +1000 [thread overview]
Message-ID: <CAKmqyKMHeqia5_1+VXd1+2RPq7-uqFVTfcFgDb7kVetgbXyNXQ@mail.gmail.com> (raw)
In-Reply-To: <CAE_xrPgiy+OrehPrzt0OZq97jkxGgnBSkEQWbKhROU+v65ac2A@mail.gmail.com>
On Thu, Oct 28, 2021 at 6:22 PM Frank Chang <frank.chang@sifive.com> wrote:
>
> On Thu, Oct 28, 2021 at 12:45 PM Alistair Francis <alistair.francis@opensource.wdc.com> wrote:
>>
>> From: Chih-Min Chao <chihmin.chao@sifive.com>
>>
>> The sNaN propagation behavior has been changed since
>> cd20cee7 in https://github.com/riscv/riscv-isa-manual.
>>
>> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
>> Signed-off-by: Frank Chang <frank.chang@sifive.com>
>> Acked-by: Alistair Francis <alistair.francis@wdc.com>
>> Message-id: 20211016085428.3001501-3-frank.chang@sifive.com
>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> ---
>> target/riscv/fpu_helper.c | 16 ++++++++++++----
>> 1 file changed, 12 insertions(+), 4 deletions(-)
>>
>> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
>> index 8700516a14..d62f470900 100644
>> --- a/target/riscv/fpu_helper.c
>> +++ b/target/riscv/fpu_helper.c
>> @@ -174,14 +174,18 @@ uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
>> {
>> float32 frs1 = check_nanbox_s(rs1);
>> float32 frs2 = check_nanbox_s(rs2);
>> - return nanbox_s(float32_minnum(frs1, frs2, &env->fp_status));
>> + return nanbox_s(env->priv_ver < PRIV_VERSION_1_11_0 ?
>> + float32_minnum(frs1, frs2, &env->fp_status) :
>> + float32_minimum_number(frs1, frs2, &env->fp_status));
>> }
>>
>> uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
>> {
>> float32 frs1 = check_nanbox_s(rs1);
>> float32 frs2 = check_nanbox_s(rs2);
>> - return nanbox_s(float32_maxnum(frs1, frs2, &env->fp_status));
>> + return nanbox_s(env->priv_ver < PRIV_VERSION_1_11_0 ?
>> + float32_maxnum(frs1, frs2, &env->fp_status) :
>> + float32_maximum_number(frs1, frs2, &env->fp_status));
>> }
>>
>> uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1)
>> @@ -283,12 +287,16 @@ uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
>>
>> uint64_t helper_fmin_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
>> {
>> - return float64_minnum(frs1, frs2, &env->fp_status);
>> + return env->priv_ver < PRIV_VERSION_1_11_0 ?
>> + float64_minnum(frs1, frs2, &env->fp_status) :
>> + float64_minimum_number(frs1, frs2, &env->fp_status);
>> }
>>
>> uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
>> {
>> - return float64_maxnum(frs1, frs2, &env->fp_status);
>> + return env->priv_ver < PRIV_VERSION_1_11_0 ?
>> + float64_maxnum(frs1, frs2, &env->fp_status) :
>> + float64_maximum_number(frs1, frs2, &env->fp_status);
>> }
>>
>> uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1)
>> --
>> 2.31.1
>>
>
> Hi Alistair,
>
> Did you pull the latest v5 patchset?
> https://lists.nongnu.org/archive/html/qemu-riscv/2021-10/msg00557.html
Strange, I don't see it on the patches list. All I see is v4
Alistair
>
> I added more texts in the commit message to describe why we tie RVF version with Priv version.
> I think it's still okay to pull this one as I don't think there's any functional changes, IIRC.
>
> Regards,
> Frank Chang
next prev parent reply other threads:[~2021-10-28 11:33 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-28 4:43 [PULL 00/18] riscv-to-apply queue Alistair Francis
2021-10-28 4:43 ` [PULL 01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
2021-10-28 4:43 ` [PULL 02/18] hw/riscv: boot: Add a PLIC config string function Alistair Francis
2021-10-28 4:43 ` [PULL 03/18] hw/riscv: sifive_u: Use the PLIC config helper function Alistair Francis
2021-10-28 4:43 ` [PULL 04/18] hw/riscv: microchip_pfsoc: " Alistair Francis
2021-10-28 4:43 ` [PULL 05/18] hw/riscv: virt: " Alistair Francis
2021-10-28 4:43 ` [PULL 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses Alistair Francis
2021-10-28 4:43 ` [PULL 07/18] target/riscv: Add J-extension into RISC-V Alistair Francis
2021-10-28 4:43 ` [PULL 08/18] target/riscv: Add CSR defines for RISC-V PM extension Alistair Francis
2021-10-28 4:43 ` [PULL 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode Alistair Francis
2021-10-28 4:43 ` [PULL 10/18] target/riscv: Add J extension state description Alistair Francis
2021-10-28 4:43 ` [PULL 11/18] target/riscv: Print new PM CSRs in QEMU logs Alistair Francis
2021-10-28 4:43 ` [PULL 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alistair Francis
2021-10-28 4:43 ` [PULL 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension Alistair Francis
2021-10-28 4:43 ` [PULL 14/18] target/riscv: Allow experimental J-ext to be turned on Alistair Francis
2021-10-28 4:43 ` [PULL 15/18] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin Alistair Francis
2021-10-28 4:43 ` [PULL 16/18] target/riscv: change the api for RVF/RVD fmin/fmax Alistair Francis
2021-10-28 8:22 ` Frank Chang
2021-10-28 11:30 ` Alistair Francis [this message]
2021-10-28 14:22 ` Richard Henderson
2021-10-28 21:40 ` Alistair Francis
2021-10-28 4:43 ` [PULL 17/18] target/riscv: fix VS interrupts forwarding to HS Alistair Francis
2021-10-28 4:43 ` [PULL 18/18] target/riscv: remove force HS exception Alistair Francis
2021-10-28 16:54 ` [PULL 00/18] riscv-to-apply queue Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAKmqyKMHeqia5_1+VXd1+2RPq7-uqFVTfcFgDb7kVetgbXyNXQ@mail.gmail.com \
--to=alistair23@gmail.com \
--cc=alistair.francis@opensource.wdc.com \
--cc=alistair.francis@wdc.com \
--cc=chihmin.chao@sifive.com \
--cc=frank.chang@sifive.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).