From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH] target/riscv: machine: Sort the .subsections
Date: Mon, 1 Nov 2021 16:52:27 +1000 [thread overview]
Message-ID: <CAKmqyKMHzqfyTN4AzACe_-j+1+FrcrvaPmcYTrAOubFuQJoaUQ@mail.gmail.com> (raw)
In-Reply-To: <20211030030606.32297-1-bmeng.cn@gmail.com>
On Sat, Oct 30, 2021 at 1:07 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Move the codes around so that the order of .subsections matches
> the one they are referenced in vmstate_riscv_cpu.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> target/riscv/machine.c | 92 +++++++++++++++++++++---------------------
> 1 file changed, 46 insertions(+), 46 deletions(-)
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 7b4c739564..ad8248ebfd 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -76,20 +76,50 @@ static bool hyper_needed(void *opaque)
> return riscv_has_ext(env, RVH);
> }
>
> -static bool vector_needed(void *opaque)
> -{
> - RISCVCPU *cpu = opaque;
> - CPURISCVState *env = &cpu->env;
> +static const VMStateDescription vmstate_hyper = {
> + .name = "cpu/hyper",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .needed = hyper_needed,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINTTL(env.hstatus, RISCVCPU),
> + VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
> + VMSTATE_UINTTL(env.hideleg, RISCVCPU),
> + VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
> + VMSTATE_UINTTL(env.htval, RISCVCPU),
> + VMSTATE_UINTTL(env.htinst, RISCVCPU),
> + VMSTATE_UINTTL(env.hgatp, RISCVCPU),
> + VMSTATE_UINT64(env.htimedelta, RISCVCPU),
>
> - return riscv_has_ext(env, RVV);
> -}
> + VMSTATE_UINT64(env.vsstatus, RISCVCPU),
> + VMSTATE_UINTTL(env.vstvec, RISCVCPU),
> + VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
> + VMSTATE_UINTTL(env.vsepc, RISCVCPU),
> + VMSTATE_UINTTL(env.vscause, RISCVCPU),
> + VMSTATE_UINTTL(env.vstval, RISCVCPU),
> + VMSTATE_UINTTL(env.vsatp, RISCVCPU),
>
> -static bool pointermasking_needed(void *opaque)
> + VMSTATE_UINTTL(env.mtval2, RISCVCPU),
> + VMSTATE_UINTTL(env.mtinst, RISCVCPU),
> +
> + VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
> + VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
> + VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
> + VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
> + VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
> + VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
> + VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
> +
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static bool vector_needed(void *opaque)
> {
> RISCVCPU *cpu = opaque;
> CPURISCVState *env = &cpu->env;
>
> - return riscv_has_ext(env, RVJ);
> + return riscv_has_ext(env, RVV);
> }
>
> static const VMStateDescription vmstate_vector = {
> @@ -108,6 +138,14 @@ static const VMStateDescription vmstate_vector = {
> }
> };
>
> +static bool pointermasking_needed(void *opaque)
> +{
> + RISCVCPU *cpu = opaque;
> + CPURISCVState *env = &cpu->env;
> +
> + return riscv_has_ext(env, RVJ);
> +}
> +
> static const VMStateDescription vmstate_pointermasking = {
> .name = "cpu/pointer_masking",
> .version_id = 1,
> @@ -126,44 +164,6 @@ static const VMStateDescription vmstate_pointermasking = {
> }
> };
>
> -static const VMStateDescription vmstate_hyper = {
> - .name = "cpu/hyper",
> - .version_id = 1,
> - .minimum_version_id = 1,
> - .needed = hyper_needed,
> - .fields = (VMStateField[]) {
> - VMSTATE_UINTTL(env.hstatus, RISCVCPU),
> - VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
> - VMSTATE_UINTTL(env.hideleg, RISCVCPU),
> - VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
> - VMSTATE_UINTTL(env.htval, RISCVCPU),
> - VMSTATE_UINTTL(env.htinst, RISCVCPU),
> - VMSTATE_UINTTL(env.hgatp, RISCVCPU),
> - VMSTATE_UINT64(env.htimedelta, RISCVCPU),
> -
> - VMSTATE_UINT64(env.vsstatus, RISCVCPU),
> - VMSTATE_UINTTL(env.vstvec, RISCVCPU),
> - VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
> - VMSTATE_UINTTL(env.vsepc, RISCVCPU),
> - VMSTATE_UINTTL(env.vscause, RISCVCPU),
> - VMSTATE_UINTTL(env.vstval, RISCVCPU),
> - VMSTATE_UINTTL(env.vsatp, RISCVCPU),
> -
> - VMSTATE_UINTTL(env.mtval2, RISCVCPU),
> - VMSTATE_UINTTL(env.mtinst, RISCVCPU),
> -
> - VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
> - VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
> - VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
> - VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
> - VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
> - VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
> - VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
> -
> - VMSTATE_END_OF_LIST()
> - }
> -};
> -
> const VMStateDescription vmstate_riscv_cpu = {
> .name = "cpu",
> .version_id = 3,
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2021-11-01 6:54 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-30 3:06 [PATCH] target/riscv: machine: Sort the .subsections Bin Meng
2021-11-01 6:52 ` Alistair Francis [this message]
2021-11-03 21:52 ` Alistair Francis
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