From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [PATCH v4 14/20] target/riscv: Adjust vsetvl according to XLEN
Date: Fri, 19 Nov 2021 22:40:44 +1000 [thread overview]
Message-ID: <CAKmqyKMK7Zb3hiXect67Mo32UP_dAd_CRoGu8hpmng-ZWcyasA@mail.gmail.com> (raw)
In-Reply-To: <20211111155149.58172-15-zhiwei_liu@c-sky.com>
On Fri, Nov 12, 2021 at 2:14 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/helper.h | 2 +-
> target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
> target/riscv/vector_helper.c | 8 +++++---
> 3 files changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index c5098380dd..f2910f5f30 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -82,7 +82,7 @@ DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl)
> #endif
>
> /* Vector functions */
> -DEF_HELPER_3(vsetvl, tl, env, tl, tl)
> +DEF_HELPER_4(vsetvl, tl, env, tl, tl, i32)
> DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32)
> DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32)
> DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32)
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 17ee3babef..6fa673f4b2 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -37,7 +37,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
> } else {
> s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
> }
> - gen_helper_vsetvl(dst, cpu_env, s1, s2);
> + gen_helper_vsetvl(dst, cpu_env, s1, s2, tcg_constant_i32(get_xlen(ctx)));
> gen_set_gpr(ctx, a->rd, dst);
>
> tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
> @@ -64,7 +64,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
> } else {
> s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
> }
> - gen_helper_vsetvl(dst, cpu_env, s1, s2);
> + gen_helper_vsetvl(dst, cpu_env, s1, s2, tcg_constant_i32(get_xlen(ctx)));
> gen_set_gpr(ctx, a->rd, dst);
>
> gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index b02ccefa4d..e49b431610 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -27,14 +27,16 @@
> #include <math.h>
>
> target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> - target_ulong s2)
> + target_ulong s2, uint32_t xlen)
> {
> int vlmax, vl;
> RISCVCPU *cpu = env_archcpu(env);
> uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
> uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
> - bool vill = FIELD_EX64(s2, VTYPE, VILL);
> - target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
> + bool vill = (s2 >> (xlen - 1)) & 0x1;
> + target_ulong reserved = s2 &
> + MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
> + xlen - 1 - R_VTYPE_RESERVED_SHIFT);
>
> if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
> /* only set vill bit. */
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2021-11-19 12:45 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-11 15:51 [PATCH v4 00/20] Support UXL filed in xstatus LIU Zhiwei
2021-11-11 15:51 ` [PATCH v4 01/20] target/riscv: Don't save pc when exception return LIU Zhiwei
2021-11-15 4:25 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 02/20] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-15 4:26 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-15 4:27 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 04/20] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-16 0:08 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 05/20] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-16 3:12 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 06/20] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-16 3:13 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 07/20] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2021-11-16 3:14 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 08/20] target/riscv: Create current pm fields in env LIU Zhiwei
2021-11-19 4:22 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2021-11-19 4:29 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 10/20] target/riscv: Calculate address according to XLEN LIU Zhiwei
2021-11-19 4:32 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 11/20] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2021-11-19 4:51 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 12/20] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-19 4:55 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 13/20] target/riscv: Fix RESERVED field length in VTYPE LIU Zhiwei
2021-11-19 4:56 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 14/20] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2021-11-19 12:40 ` Alistair Francis [this message]
2021-11-11 15:51 ` [PATCH v4 15/20] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2021-11-19 12:33 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 16/20] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-19 12:34 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 17/20] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-19 12:42 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 18/20] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-19 12:46 ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 19/20] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-11 15:51 ` [PATCH v4 20/20] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-11 18:23 ` Richard Henderson
2021-11-19 12:55 ` Alistair Francis
2021-11-19 12:57 ` [PATCH v4 00/20] Support UXL filed in xstatus Alistair Francis
2021-11-19 13:44 ` LIU Zhiwei
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