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From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: Frank Chang <frank.chang@sifive.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
Date: Thu, 22 Apr 2021 11:42:25 +1000	[thread overview]
Message-ID: <CAKmqyKMKrNtqULUdQTdXAoHX8JS_dcRAQYx2MPbMiRtzJt6DWw@mail.gmail.com> (raw)
In-Reply-To: <3b6b4967-d9bc-ec4f-4676-cb9df2b4930a@linaro.org>

On Thu, Apr 22, 2021 at 11:06 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 4/19/21 6:31 PM, frank.chang@sifive.com wrote:
> > +    return 3; /* deafult NaN */
>
> Late notice of spelling error: default.

Fixed when I applied it.

Thanks!

Applied to riscv-to-apply.next

Alistair

>
> r~
>


      reply	other threads:[~2021-04-22  1:45 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-20  1:31 [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions frank.chang
2021-04-20 14:17 ` Richard Henderson
2021-04-22  0:05   ` Alistair Francis
2021-04-22  1:06 ` Richard Henderson
2021-04-22  1:42   ` Alistair Francis [this message]

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