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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::92e; envelope-from=alistair23@gmail.com; helo=mail-ua1-x92e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Sep 25, 2023 at 7:17=E2=80=AFPM Daniel Henrique Barboza wrote: > > > > On 9/22/23 02:29, Alistair Francis wrote: > > On Wed, Sep 20, 2023 at 9:24=E2=80=AFPM Daniel Henrique Barboza > > wrote: > >> > >> riscv_cpu_realize_tcg() was added to allow TCG cpus to have a differen= t > >> realize() path during the common riscv_cpu_realize(), making it a good > >> choice to start moving TCG exclusive code to tcg-cpu.c. > >> > >> Rename it to tcg_cpu_realizefn() and assign it as a implementation of > >> accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during > >> riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar > >> approach with KVM in the near future. > >> > >> riscv_cpu_validate_set_extensions() is too big and with too many > >> dependencies to be moved in this same patch. We'll do that next. > >> > >> Signed-off-by: Daniel Henrique Barboza > >> Reviewed-by: Andrew Jones > >> Reviewed-by: LIU Zhiwei > >> --- > >> target/riscv/cpu.c | 128 ----------------------------------- > >> target/riscv/tcg/tcg-cpu.c | 133 +++++++++++++++++++++++++++++++++++= ++ > >> 2 files changed, 133 insertions(+), 128 deletions(-) > >> > >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > >> index e72c49c881..030629294f 100644 > >> --- a/target/riscv/cpu.c > >> +++ b/target/riscv/cpu.c > >> @@ -23,9 +23,7 @@ > >> #include "qemu/log.h" > >> #include "cpu.h" > >> #include "cpu_vendorid.h" > >> -#include "pmu.h" > >> #include "internals.h" > >> -#include "time_helper.h" > >> #include "exec/exec-all.h" > >> #include "qapi/error.h" > >> #include "qapi/visitor.h" > >> @@ -1064,29 +1062,6 @@ static void riscv_cpu_validate_v(CPURISCVState = *env, RISCVCPUConfig *cfg, > >> } > >> } > >> > >> -static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) > >> -{ > >> - CPURISCVState *env =3D &cpu->env; > >> - int priv_version =3D -1; > >> - > >> - if (cpu->cfg.priv_spec) { > >> - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { > >> - priv_version =3D PRIV_VERSION_1_12_0; > >> - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { > >> - priv_version =3D PRIV_VERSION_1_11_0; > >> - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { > >> - priv_version =3D PRIV_VERSION_1_10_0; > >> - } else { > >> - error_setg(errp, > >> - "Unsupported privilege spec version '%s'", > >> - cpu->cfg.priv_spec); > >> - return; > >> - } > >> - > >> - env->priv_ver =3D priv_version; > >> - } > >> -} > >> - > >> static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) > >> { > >> CPURISCVState *env =3D &cpu->env; > >> @@ -1111,33 +1086,6 @@ static void riscv_cpu_disable_priv_spec_isa_ext= s(RISCVCPU *cpu) > >> } > >> } > >> > >> -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) > >> -{ > >> - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); > >> - CPUClass *cc =3D CPU_CLASS(mcc); > >> - CPURISCVState *env =3D &cpu->env; > >> - > >> - /* Validate that MISA_MXL is set properly. */ > >> - switch (env->misa_mxl_max) { > >> -#ifdef TARGET_RISCV64 > >> - case MXL_RV64: > >> - case MXL_RV128: > >> - cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; > >> - break; > >> -#endif > >> - case MXL_RV32: > >> - cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; > >> - break; > >> - default: > >> - g_assert_not_reached(); > >> - } > >> - > >> - if (env->misa_mxl_max !=3D env->misa_mxl) { > >> - error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); > >> - return; > >> - } > >> -} > >> - > >> /* > >> * Check consistency between chosen extensions while setting > >> * cpu->cfg accordingly. > >> @@ -1511,74 +1459,6 @@ static void riscv_cpu_finalize_features(RISCVCP= U *cpu, Error **errp) > >> #endif > >> } > >> > >> -static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **= errp) > >> -{ > >> - if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_= 0) { > >> - error_setg(errp, "H extension requires priv spec 1.12.0"); > >> - return; > >> - } > >> -} > >> - > >> -static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) > >> -{ > >> - RISCVCPU *cpu =3D RISCV_CPU(dev); > >> - CPURISCVState *env =3D &cpu->env; > >> - Error *local_err =3D NULL; > >> - > >> - if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) { > >> - error_setg(errp, "'host' CPU is not compatible with TCG accel= eration"); > >> - return; > >> - } > >> - > >> - riscv_cpu_validate_misa_mxl(cpu, &local_err); > >> - if (local_err !=3D NULL) { > >> - error_propagate(errp, local_err); > >> - return; > >> - } > >> - > >> - riscv_cpu_validate_priv_spec(cpu, &local_err); > >> - if (local_err !=3D NULL) { > >> - error_propagate(errp, local_err); > >> - return; > >> - } > >> - > >> - riscv_cpu_validate_misa_priv(env, &local_err); > >> - if (local_err !=3D NULL) { > >> - error_propagate(errp, local_err); > >> - return; > >> - } > >> - > >> - if (cpu->cfg.epmp && !cpu->cfg.pmp) { > >> - /* > >> - * Enhanced PMP should only be available > >> - * on harts with PMP support > >> - */ > >> - error_setg(errp, "Invalid configuration: EPMP requires PMP su= pport"); > >> - return; > >> - } > >> - > >> - riscv_cpu_validate_set_extensions(cpu, &local_err); > >> - if (local_err !=3D NULL) { > >> - error_propagate(errp, local_err); > >> - return; > >> - } > >> - > >> -#ifndef CONFIG_USER_ONLY > >> - CPU(dev)->tcg_cflags |=3D CF_PCREL; > >> - > >> - if (cpu->cfg.ext_sstc) { > >> - riscv_timer_init(cpu); > >> - } > >> - > >> - if (cpu->cfg.pmu_num) { > >> - if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_ss= cofpmf) { > >> - cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, > >> - riscv_pmu_timer_cb, cpu); > >> - } > >> - } > >> -#endif > >> -} > >> - > >> static void riscv_cpu_realize(DeviceState *dev, Error **errp) > >> { > >> CPUState *cs =3D CPU(dev); > >> @@ -1597,14 +1477,6 @@ static void riscv_cpu_realize(DeviceState *dev,= Error **errp) > >> return; > >> } > >> > >> - if (tcg_enabled()) { > >> - riscv_cpu_realize_tcg(dev, &local_err); > >> - if (local_err !=3D NULL) { > >> - error_propagate(errp, local_err); > >> - return; > >> - } > >> - } > >> - > >> riscv_cpu_finalize_features(cpu, &local_err); > >> if (local_err !=3D NULL) { > >> error_propagate(errp, local_err); > >> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > >> index 0326cead0d..f47dc2064f 100644 > >> --- a/target/riscv/tcg/tcg-cpu.c > >> +++ b/target/riscv/tcg/tcg-cpu.c > >> @@ -18,10 +18,142 @@ > >> */ > > > > I do think we should keep the Copyright statements from cpu.c in this > > new file as you are now copying across the majority of code from there > > I don't mind keeping the copyright statements from cpu.c here. Feel free = to change it > in tree (or let me know if you want me to re-send). Whoops. I missed this comment. Do you mind sending a v4 then I will apply t= hat Alistair