From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v4 11/21] target/riscv: Add DisasExtend to gen_unary
Date: Mon, 23 Aug 2021 16:15:33 +1000 [thread overview]
Message-ID: <CAKmqyKMO7Z5TpQhHukFPA-GabuVTAMbsfWw5-RYmes5Mf-+GBg@mail.gmail.com> (raw)
In-Reply-To: <20210820174257.548286-12-richard.henderson@linaro.org>
On Sat, Aug 21, 2021 at 3:50 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Use ctx->w for ctpopw, which is the only one that can
> re-use the generic algorithm for the narrow operation.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 14 ++++++--------
> target/riscv/insn_trans/trans_rvb.c.inc | 24 +++++++++---------------
> 2 files changed, 15 insertions(+), 23 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 09853530c4..785e9e58cc 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -478,17 +478,15 @@ static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
> return true;
> }
>
> -static bool gen_unary(DisasContext *ctx, arg_r2 *a,
> - void(*func)(TCGv, TCGv))
> +static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
> + void (*func)(TCGv, TCGv))
> {
> - TCGv source = tcg_temp_new();
> + TCGv dest = dest_gpr(ctx, a->rd);
> + TCGv src1 = get_gpr(ctx, a->rs1, ext);
>
> - gen_get_gpr(ctx, source, a->rs1);
> + func(dest, src1);
>
> - (*func)(source, source);
> -
> - gen_set_gpr(ctx, a->rd, source);
> - tcg_temp_free(source);
> + gen_set_gpr(ctx, a->rd, dest);
> return true;
> }
>
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index 73f088be23..e255678fff 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -26,7 +26,7 @@ static void gen_clz(TCGv ret, TCGv arg1)
> static bool trans_clz(DisasContext *ctx, arg_clz *a)
> {
> REQUIRE_EXT(ctx, RVB);
> - return gen_unary(ctx, a, gen_clz);
> + return gen_unary(ctx, a, EXT_ZERO, gen_clz);
> }
>
> static void gen_ctz(TCGv ret, TCGv arg1)
> @@ -37,13 +37,13 @@ static void gen_ctz(TCGv ret, TCGv arg1)
> static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
> {
> REQUIRE_EXT(ctx, RVB);
> - return gen_unary(ctx, a, gen_ctz);
> + return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
> }
>
> static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
> {
> REQUIRE_EXT(ctx, RVB);
> - return gen_unary(ctx, a, tcg_gen_ctpop_tl);
> + return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
> }
>
> static bool trans_andn(DisasContext *ctx, arg_andn *a)
> @@ -132,13 +132,13 @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
> static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
> {
> REQUIRE_EXT(ctx, RVB);
> - return gen_unary(ctx, a, tcg_gen_ext8s_tl);
> + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
> }
>
> static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
> {
> REQUIRE_EXT(ctx, RVB);
> - return gen_unary(ctx, a, tcg_gen_ext16s_tl);
> + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
> }
>
> static void gen_sbop_mask(TCGv ret, TCGv shamt)
> @@ -366,7 +366,6 @@ GEN_TRANS_SHADD(3)
>
> static void gen_clzw(TCGv ret, TCGv arg1)
> {
> - tcg_gen_ext32u_tl(ret, arg1);
> tcg_gen_clzi_tl(ret, ret, 64);
> tcg_gen_subi_tl(ret, ret, 32);
> }
> @@ -375,7 +374,7 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVB);
> - return gen_unary(ctx, a, gen_clzw);
> + return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
> }
>
> static void gen_ctzw(TCGv ret, TCGv arg1)
> @@ -388,20 +387,15 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVB);
> - return gen_unary(ctx, a, gen_ctzw);
> -}
> -
> -static void gen_cpopw(TCGv ret, TCGv arg1)
> -{
> - tcg_gen_ext32u_tl(arg1, arg1);
> - tcg_gen_ctpop_tl(ret, arg1);
> + return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
> }
>
> static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVB);
> - return gen_unary(ctx, a, gen_cpopw);
> + ctx->w = true;
> + return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
> }
>
> static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2021-08-23 6:17 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-20 17:42 [PATCH v4 00/21] target/riscv: Use tcg_constant_* Richard Henderson
2021-08-20 17:42 ` [PATCH v4 01/21] " Richard Henderson
2021-08-20 17:42 ` [PATCH v4 02/21] tests/tcg/riscv64: Add test for division Richard Henderson
2021-08-23 3:18 ` Bin Meng
2021-08-23 6:04 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 03/21] target/riscv: Clean up division helpers Richard Henderson
2021-08-23 4:07 ` Bin Meng
2021-08-23 6:09 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 04/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr Richard Henderson
2021-08-20 17:42 ` [PATCH v4 05/21] target/riscv: Introduce DisasExtend and new helpers Richard Henderson
2021-08-20 17:42 ` [PATCH v4 06/21] target/riscv: Add DisasExtend to gen_arith* Richard Henderson
2021-08-20 17:42 ` [PATCH v4 07/21] target/riscv: Remove gen_arith_div* Richard Henderson
2021-08-20 17:42 ` [PATCH v4 08/21] target/riscv: Use gen_arith for mulh and mulhu Richard Henderson
2021-08-20 17:42 ` [PATCH v4 09/21] target/riscv: Move gen_* helpers for RVM Richard Henderson
2021-08-20 17:42 ` [PATCH v4 10/21] target/riscv: Move gen_* helpers for RVB Richard Henderson
2021-08-23 6:13 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 11/21] target/riscv: Add DisasExtend to gen_unary Richard Henderson
2021-08-23 6:15 ` Alistair Francis [this message]
2021-08-20 17:42 ` [PATCH v4 12/21] target/riscv: Use DisasExtend in shift operations Richard Henderson
2021-08-23 6:18 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 13/21] target/riscv: Use get_gpr in branches Richard Henderson
2021-08-23 6:19 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 14/21] target/riscv: Use {get, dest}_gpr for integer load/store Richard Henderson
2021-08-23 7:04 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 15/21] target/riscv: Reorg csr instructions Richard Henderson
2021-08-23 4:54 ` Bin Meng
2021-08-23 19:54 ` Richard Henderson
2021-08-20 17:42 ` [PATCH v4 16/21] target/riscv: Use {get,dest}_gpr for RVA Richard Henderson
2021-08-20 17:42 ` [PATCH v4 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw Richard Henderson
2021-08-20 17:42 ` [PATCH v4 18/21] target/riscv: Use {get,dest}_gpr for RVF Richard Henderson
2021-08-20 17:42 ` [PATCH v4 19/21] target/riscv: Use {get,dest}_gpr for RVD Richard Henderson
2021-08-20 17:42 ` [PATCH v4 20/21] target/riscv: Tidy trans_rvh.c.inc Richard Henderson
2021-08-20 17:42 ` [PATCH v4 21/21] target/riscv: Use {get,dest}_gpr for RVV Richard Henderson
2021-08-30 10:12 ` [PATCH v4 00/21] target/riscv: Use tcg_constant_* Alistair Francis
2021-08-30 15:26 ` Richard Henderson
2021-08-31 0:20 ` Alistair Francis
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