qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, dbarboza@ventanamicro.com
Subject: Re: [PATCH 07/11] tcg/riscv: Support REV8 from Zbb
Date: Wed, 17 May 2023 09:50:31 +1000	[thread overview]
Message-ID: <CAKmqyKMQETHCjF-U_2D2f2HAioq-_pmC7xXbPMhpap3dCqANjQ@mail.gmail.com> (raw)
In-Reply-To: <20230503085657.1814850-8-richard.henderson@linaro.org>

On Wed, May 3, 2023 at 6:59 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  tcg/riscv/tcg-target.h     | 10 +++++-----
>  tcg/riscv/tcg-target.c.inc | 29 +++++++++++++++++++++++++++++
>  2 files changed, 34 insertions(+), 5 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
> index 317d385924..8e327afc3a 100644
> --- a/tcg/riscv/tcg-target.h
> +++ b/tcg/riscv/tcg-target.h
> @@ -116,8 +116,8 @@ extern bool have_zbb;
>  #define TCG_TARGET_HAS_ext16s_i32       1
>  #define TCG_TARGET_HAS_ext8u_i32        1
>  #define TCG_TARGET_HAS_ext16u_i32       1
> -#define TCG_TARGET_HAS_bswap16_i32      0
> -#define TCG_TARGET_HAS_bswap32_i32      0
> +#define TCG_TARGET_HAS_bswap16_i32      have_zbb
> +#define TCG_TARGET_HAS_bswap32_i32      have_zbb
>  #define TCG_TARGET_HAS_not_i32          1
>  #define TCG_TARGET_HAS_neg_i32          1
>  #define TCG_TARGET_HAS_andc_i32         have_zbb
> @@ -149,9 +149,9 @@ extern bool have_zbb;
>  #define TCG_TARGET_HAS_ext8u_i64        1
>  #define TCG_TARGET_HAS_ext16u_i64       1
>  #define TCG_TARGET_HAS_ext32u_i64       1
> -#define TCG_TARGET_HAS_bswap16_i64      0
> -#define TCG_TARGET_HAS_bswap32_i64      0
> -#define TCG_TARGET_HAS_bswap64_i64      0
> +#define TCG_TARGET_HAS_bswap16_i64      have_zbb
> +#define TCG_TARGET_HAS_bswap32_i64      have_zbb
> +#define TCG_TARGET_HAS_bswap64_i64      have_zbb
>  #define TCG_TARGET_HAS_not_i64          1
>  #define TCG_TARGET_HAS_neg_i64          1
>  #define TCG_TARGET_HAS_andc_i64         have_zbb
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 58f969b4fe..9cbefb2833 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -1488,6 +1488,30 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
>          }
>          break;
>
> +    case INDEX_op_bswap64_i64:
> +        tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
> +        break;
> +    case INDEX_op_bswap32_i32:
> +        a2 = 0;
> +        /* fall through */
> +    case INDEX_op_bswap32_i64:
> +        tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
> +        if (a2 & TCG_BSWAP_OZ) {
> +            tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 32);
> +        } else {
> +            tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 32);
> +        }
> +        break;
> +    case INDEX_op_bswap16_i64:
> +    case INDEX_op_bswap16_i32:
> +        tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
> +        if (a2 & TCG_BSWAP_OZ) {
> +            tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 48);
> +        } else {
> +            tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 48);
> +        }
> +        break;
> +
>      case INDEX_op_add2_i32:
>          tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
>                          const_args[4], const_args[5], false, true);
> @@ -1605,6 +1629,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
>      case INDEX_op_extrl_i64_i32:
>      case INDEX_op_extrh_i64_i32:
>      case INDEX_op_ext_i32_i64:
> +    case INDEX_op_bswap16_i32:
> +    case INDEX_op_bswap32_i32:
> +    case INDEX_op_bswap16_i64:
> +    case INDEX_op_bswap32_i64:
> +    case INDEX_op_bswap64_i64:
>          return C_O1_I1(r, r);
>
>      case INDEX_op_st8_i32:
> --
> 2.34.1
>
>


  parent reply	other threads:[~2023-05-16 23:51 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-03  8:56 [PATCH 00/11] tcg/riscv: Support for Zba, Zbb, Zicond extensions Richard Henderson
2023-05-03  8:56 ` [PATCH 01/11] disas/riscv: Decode czero.{eqz,nez} Richard Henderson
2023-05-08 12:37   ` Daniel Henrique Barboza
2023-05-16 23:33   ` Alistair Francis
2023-05-03  8:56 ` [PATCH 02/11] tcg/riscv: Probe for Zba, Zbb, Zicond extensions Richard Henderson
2023-05-08 12:37   ` Daniel Henrique Barboza
2023-05-16 23:35   ` Alistair Francis
2023-05-03  8:56 ` [PATCH 03/11] tcg/riscv: Support ANDN, ORN, XNOR from Zbb Richard Henderson
2023-05-08 12:37   ` Daniel Henrique Barboza
2023-05-16 23:38   ` Alistair Francis
2023-05-03  8:56 ` [PATCH 04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb Richard Henderson
2023-05-08 12:39   ` Daniel Henrique Barboza
2023-05-16 23:40   ` Alistair Francis
2023-05-03  8:56 ` [PATCH 05/11] tcg/riscv: Use ADD.UW for guest address generation Richard Henderson
2023-05-08 12:43   ` Daniel Henrique Barboza
2023-05-16 23:43   ` Alistair Francis
2023-05-03  8:56 ` [PATCH 06/11] tcg/riscv: Support rotates from Zbb Richard Henderson
2023-05-08 12:44   ` Daniel Henrique Barboza
2023-05-16 23:48   ` Alistair Francis
2023-05-03  8:56 ` [PATCH 07/11] tcg/riscv: Support REV8 " Richard Henderson
2023-05-08 12:45   ` Daniel Henrique Barboza
2023-05-16 23:50   ` Alistair Francis [this message]
2023-05-03  8:56 ` [PATCH 08/11] tcg/riscv: Support CPOP " Richard Henderson
2023-05-08 12:45   ` Daniel Henrique Barboza
2023-05-16 23:50   ` Alistair Francis
2023-05-03  8:56 ` [PATCH 09/11] tcg/riscv: Improve setcond expansion Richard Henderson
2023-05-08 12:46   ` Daniel Henrique Barboza
2023-05-17  0:16   ` Alistair Francis
2023-05-03  8:56 ` [PATCH 10/11] tcg/riscv: Implement movcond Richard Henderson
2023-05-08 12:47   ` Daniel Henrique Barboza
2023-05-17  0:19   ` Alistair Francis
2023-05-03  8:56 ` [PATCH 11/11] tcg/riscv: Support CTZ, CLZ from Zbb Richard Henderson
2023-05-08 12:47   ` Daniel Henrique Barboza
2023-05-17  1:47   ` Alistair Francis
2023-05-08 12:53 ` [PATCH 00/11] tcg/riscv: Support for Zba, Zbb, Zicond extensions Daniel Henrique Barboza

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAKmqyKMQETHCjF-U_2D2f2HAioq-_pmC7xXbPMhpap3dCqANjQ@mail.gmail.com \
    --to=alistair23@gmail.com \
    --cc=dbarboza@ventanamicro.com \
    --cc=qemu-devel@nongnu.org \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).