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From: Alistair Francis <alistair23@gmail.com>
Date: Tue, 20 Nov 2018 15:22:09 -0800
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Subject: Re: [Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the target
 init code
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To: Richard Henderson <richard.henderson@linaro.org>
Cc: Alistair Francis <Alistair.Francis@wdc.com>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, qemu-riscv@nongnu.org

On Mon, Nov 19, 2018 at 10:55 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 11/20/18 12:04 AM, Alistair Francis wrote:
> > On Fri, Nov 16, 2018 at 9:26 AM Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >>
> >> On 11/15/18 11:36 PM, Alistair Francis wrote:
> >>> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_L0);
> >>> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_L1);
> >>> +    tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA);
> >>
> >> Why are these three reserved?
> >
> > Do these not need to be? I thought we had to reserve them.
>
> The return address, I presume, has been saved by the prologue.  I see no reason
> why it can't be yet another call-clobbered register.

Ok, removed.

>
> As for the other two... what are they supposed to be?

They were old temp registers. L1 wasn't even used and I have replace
L0 with TMP0 as we have enough tmp registers.

Alistair

>
>
> r~