Re: [PATCH 3/4] target/riscv: Add zcmop extension

[Alistair Francis <alistair23@gmail.com>]

On Wed, May 22, 2024 at 4:32 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> Zcmop defines eight 16-bit MOP instructions named C.MOP.n, where n is
> an odd integer between 1 and 15, inclusive. C.MOP.n is encoded in
> the reserved encoding space corresponding to C.LUI xn, 0.
>
> Unlike the MOPs defined in the Zimop extension, the C.MOP.n instructions
> are defined to not write any register.
>
> In current implementation, C.MOP.n only has an check function, without any
> other more behavior.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c                          |  2 ++
>  target/riscv/cpu_cfg.h                      |  1 +
>  target/riscv/insn16.decode                  |  1 +
>  target/riscv/insn_trans/trans_rvzcmop.c.inc | 29 +++++++++++++++++++++
>  target/riscv/tcg/tcg-cpu.c                  |  5 ++++
>  target/riscv/translate.c                    |  1 +
>  6 files changed, 39 insertions(+)
>  create mode 100644 target/riscv/insn_trans/trans_rvzcmop.c.inc
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c1ac521142..5052237a5b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -176,6 +176,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
>      ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
>      ISA_EXT_DATA_ENTRY(zimop, PRIV_VERSION_1_12_0, ext_zimop),
> +    ISA_EXT_DATA_ENTRY(zcmop, PRIV_VERSION_1_12_0, ext_zcmop),
>      ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
>      ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
>      ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
> @@ -1465,6 +1466,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>      MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
>      MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
>      MULTI_EXT_CFG_BOOL("zimop", ext_zimop, false),
> +    MULTI_EXT_CFG_BOOL("zcmop", ext_zcmop, false),
>      MULTI_EXT_CFG_BOOL("zacas", ext_zacas, false),
>      MULTI_EXT_CFG_BOOL("zaamo", ext_zaamo, false),
>      MULTI_EXT_CFG_BOOL("zalrsc", ext_zalrsc, false),
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index b547fbba9d..e29d4f6f9c 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -72,6 +72,7 @@ struct RISCVCPUConfig {
>      bool ext_zihintpause;
>      bool ext_zihpm;
>      bool ext_zimop;
> +    bool ext_zcmop;
>      bool ext_ztso;
>      bool ext_smstateen;
>      bool ext_sstc;
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index b96c534e73..3953bcf82d 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -140,6 +140,7 @@ sw                110  ... ... .. ... 00 @cs_w
>  addi              000 .  .....  ..... 01 @ci
>  addi              010 .  .....  ..... 01 @c_li
>  {
> +  c_mop_n         011 0 0 n:3 1 00000 01
>    illegal         011 0  -----  00000 01 # c.addi16sp and c.lui, RES nzimm=0
>    addi            011 .  00010  ..... 01 @c_addi16sp
>    lui             011 .  .....  ..... 01 @c_lui
> diff --git a/target/riscv/insn_trans/trans_rvzcmop.c.inc b/target/riscv/insn_trans/trans_rvzcmop.c.inc
> new file mode 100644
> index 0000000000..7205586508
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rvzcmop.c.inc
> @@ -0,0 +1,29 @@
> +/*
> + * RISC-V translation routines for compressed May-Be-Operation(zcmop).
> + *
> + * Copyright (c) 2024 Alibaba Group.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#define REQUIRE_ZCMOP(ctx) do {           \
> +    if (!ctx->cfg_ptr->ext_zcmop) {       \
> +        return false;                     \
> +    }                                     \
> +} while (0)
> +
> +static bool trans_c_mop_n(DisasContext *ctx, arg_c_mop_n *a)
> +{
> +    REQUIRE_ZCMOP(ctx);
> +    return true;
> +}
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 40054a391a..499b48dce8 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -583,6 +583,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>          }
>      }
>
> +    if (cpu->cfg.ext_zcmop && !cpu->cfg.ext_zca) {
> +        error_setg(errp, "Zcmop extensions require Zca");
> +        return;
> +    }
> +
>      if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
>          error_setg(errp, "Zcf extension is only relevant to RV32");
>          return;
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 77c6564834..51dfb03685 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1112,6 +1112,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
>  /* Include the auto-generated decoder for 16 bit insn */
>  #include "decode-insn16.c.inc"
>  #include "insn_trans/trans_rvzce.c.inc"
> +#include "insn_trans/trans_rvzcmop.c.inc"
>
>  /* Include decoders for factored-out extensions */
>  #include "decode-XVentanaCondOps.c.inc"
> --
> 2.25.1
>
>