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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::12d; envelope-from=alistair23@gmail.com; helo=mail-il1-x12d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Oct 25, 2021 at 10:55 PM Rahul Pathak wrote: > > Signed-off-by: Rahul Pathak > --- > target/riscv/cpu_bits.h | 1 + > target/riscv/csr.c | 19 +++++++++++++++---- > 2 files changed, 16 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index cffcd3a5df..e2f154b7c5 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -140,6 +140,7 @@ > #define CSR_MARCHID 0xf12 > #define CSR_MIMPID 0xf13 > #define CSR_MHARTID 0xf14 > +#define CSR_MCONFIGPTR 0xf15 > > /* Machine Trap Setup */ > #define CSR_MSTATUS 0x300 > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 69e4d65fcd..2d7f608d49 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -209,6 +209,16 @@ static RISCVException epmp(CPURISCVState *env, int csrno) > > return RISCV_EXCP_ILLEGAL_INST; > } > + > +static RISCVException priv1p12(CPURISCVState *env, int csrno) > +{ > + if (env->priv_ver >= PRIV_VERSION_1_12_0) { > + return RISCV_EXCP_NONE; > + } > + > + return RISCV_EXCP_ILLEGAL_INST; > +} > + > #endif > > /* User Floating-Point CSRs */ > @@ -1569,10 +1579,11 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, > > /* Machine Information Registers */ > - [CSR_MVENDORID] = { "mvendorid", any, read_zero }, > - [CSR_MARCHID] = { "marchid", any, read_zero }, > - [CSR_MIMPID] = { "mimpid", any, read_zero }, > - [CSR_MHARTID] = { "mhartid", any, read_mhartid }, > + [CSR_MVENDORID] = { "mvendorid", any, read_zero }, > + [CSR_MARCHID] = { "marchid", any, read_zero }, > + [CSR_MIMPID] = { "mimpid", any, read_zero }, > + [CSR_MHARTID] = { "mhartid", any, read_mhartid }, Why change these? > + [CSR_MCONFIGPTR] = {"mconfigptr", priv1p12, read_zero }, This looks fine, but there are more changes then this in v1.12. Looking at the preface we need mret/sret changes at least. It also looks like some other changes will need to be implemented or at least checked. Alistair > > /* Machine Trap Setup */ > [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus }, > -- > 2.25.1 > >