From: Alistair Francis <alistair23@gmail.com>
To: Nicholas Piggin <npiggin@gmail.com>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Laurent Vivier <laurent@vivier.eu>,
Pierrick Bouvier <pierrick.bouvier@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Richard Henderson <richard.henderson@linaro.org>,
Joel Stanley <joel@jms.id.au>
Subject: Re: [PATCH v3 3/5] linux-user/riscv: Add extended state to sigcontext
Date: Wed, 25 Mar 2026 13:14:30 +1000 [thread overview]
Message-ID: <CAKmqyKMVTjrm3-jn-hz5bsfa+TCF3yae-VcwuF7UTh_zqf5UMQ@mail.gmail.com> (raw)
In-Reply-To: <20260321141345.599105-4-npiggin@gmail.com>
On Sun, Mar 22, 2026 at 12:16 AM Nicholas Piggin <npiggin@gmail.com> wrote:
>
> Linux/riscv has extended the sigcontext with padding and an
> extended state structure that can save various optional
> features like vector in a flexible format. Update the
> linux-user signal handling to this new structure.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> linux-user/riscv/signal.c | 93 +++++++++++++++++++++++++++----
> linux-user/riscv/vdso-asmoffset.h | 4 +-
> 2 files changed, 85 insertions(+), 12 deletions(-)
>
> diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
> index ece276f85f..e20b9ac177 100644
> --- a/linux-user/riscv/signal.c
> +++ b/linux-user/riscv/signal.c
> @@ -31,14 +31,43 @@
>
> The code below is qemu re-implementation of arch/riscv/kernel/signal.c */
>
> -struct target_sigcontext {
> +struct target_gp_state {
> abi_long pc;
> abi_long gpr[31]; /* x0 is not present, so all offsets must be -1 */
> +};
> +
> +struct target_fp_state {
> uint64_t fpr[32];
> uint32_t fcsr;
> +};
> +
> +/* The Magic number for signal context frame header. */
> +#define END_MAGIC 0x0
> +
> +/* The size of END signal context header. */
> +#define END_HDR_SIZE 0x0
> +
> +struct target_ctx_hdr {
> + uint32_t magic;
> + uint32_t size;
> +};
> +
> +struct target_extra_ext_header {
> + uint32_t __padding[129] __attribute__((aligned(16)));
> + uint32_t reserved;
> + struct target_ctx_hdr hdr;
> +};
> +
> +struct target_sigcontext {
> + struct target_gp_state sc_regs;
> + union {
> + struct target_fp_state sc_fpregs;
> + struct target_extra_ext_header sc_extdesc;
> + };
> }; /* cf. riscv-linux:arch/riscv/include/uapi/asm/ptrace.h */
I would argue that arch/riscv/include/uapi/asm/sigcontext.h is a
better pointer, but both work
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> -QEMU_BUILD_BUG_ON(offsetof(struct target_sigcontext, fpr) != offsetof_freg0);
> +QEMU_BUILD_BUG_ON(offsetof(struct target_sigcontext, sc_fpregs.fpr) !=
> + offsetof_freg0);
>
> struct target_ucontext {
> abi_ulong uc_flags;
> @@ -79,19 +108,26 @@ static abi_ulong get_sigframe(struct target_sigaction *ka,
>
> static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
> {
> + struct target_ctx_hdr *hdr;
> int i;
>
> - __put_user(env->pc, &sc->pc);
> + __put_user(env->pc, &sc->sc_regs.pc);
>
> for (i = 1; i < 32; i++) {
> - __put_user(env->gpr[i], &sc->gpr[i - 1]);
> + __put_user(env->gpr[i], &sc->sc_regs.gpr[i - 1]);
> }
> for (i = 0; i < 32; i++) {
> - __put_user(env->fpr[i], &sc->fpr[i]);
> + __put_user(env->fpr[i], &sc->sc_fpregs.fpr[i]);
> }
>
> uint32_t fcsr = riscv_csr_read(env, CSR_FCSR);
> - __put_user(fcsr, &sc->fcsr);
> + __put_user(fcsr, &sc->sc_fpregs.fcsr);
> +
> + __put_user(0, &sc->sc_extdesc.reserved);
> +
> + hdr = &sc->sc_extdesc.hdr;
> + __put_user(END_MAGIC, &hdr->magic);
> + __put_user(END_HDR_SIZE, &hdr->size);
> }
>
> static void setup_ucontext(struct target_ucontext *uc,
> @@ -147,21 +183,58 @@ badframe:
>
> static bool restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
> {
> + struct target_ctx_hdr *hdr;
> + uint32_t rsv, magic, size;
> int i;
>
> - __get_user(env->pc, &sc->pc);
> + __get_user(env->pc, &sc->sc_regs.pc);
>
> for (i = 1; i < 32; ++i) {
> - __get_user(env->gpr[i], &sc->gpr[i - 1]);
> + __get_user(env->gpr[i], &sc->sc_regs.gpr[i - 1]);
> }
> for (i = 0; i < 32; ++i) {
> - __get_user(env->fpr[i], &sc->fpr[i]);
> + __get_user(env->fpr[i], &sc->sc_fpregs.fpr[i]);
> }
>
> uint32_t fcsr;
> - __get_user(fcsr, &sc->fcsr);
> + __get_user(fcsr, &sc->sc_fpregs.fcsr);
> riscv_csr_write(env, CSR_FCSR, fcsr);
>
> + hdr = &sc->sc_extdesc.hdr;
> + __get_user(rsv, &sc->sc_extdesc.reserved);
> + if (rsv != 0) {
> + qemu_log_mask(LOG_GUEST_ERROR, "signal: sigcontext reserved field is "
> + "non-zero\n");
> + return false;
> + }
> +
> + __get_user(magic, &hdr->magic);
> + while (magic != END_MAGIC) {
> + switch (magic) {
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR, "signal: unknown extended state in "
> + "sigcontext, magic=0x%08x\n", magic);
> + return false;
> + }
> +
> + __get_user(size, &hdr->size);
> + if (size == 0) {
> + qemu_log_mask(LOG_GUEST_ERROR, "signal: extended state in "
> + "sigcontext has size 0\n");
> + return false;
> + }
> +
> + hdr = (void *)hdr + size;
> + __get_user(magic, &hdr->magic);
> + }
> +
> + __get_user(size, &hdr->size);
> + if (size != END_HDR_SIZE) {
> + qemu_log_mask(LOG_GUEST_ERROR, "signal: extended state end header has "
> + "size=%u (should be 0)\n", size);
> + return false;
> + }
> +
> return true;
> }
>
> diff --git a/linux-user/riscv/vdso-asmoffset.h b/linux-user/riscv/vdso-asmoffset.h
> index 123902ef61..92e8ac10ab 100644
> --- a/linux-user/riscv/vdso-asmoffset.h
> +++ b/linux-user/riscv/vdso-asmoffset.h
> @@ -1,9 +1,9 @@
> #ifdef TARGET_ABI32
> -# define sizeof_rt_sigframe 0x2b0
> +# define sizeof_rt_sigframe 0x3b0
> # define offsetof_uc_mcontext 0x120
> # define offsetof_freg0 0x80
> #else
> -# define sizeof_rt_sigframe 0x340
> +# define sizeof_rt_sigframe 0x440
> # define offsetof_uc_mcontext 0x130
> # define offsetof_freg0 0x100
> #endif
> --
> 2.51.0
>
>
next prev parent reply other threads:[~2026-03-25 3:15 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-21 14:13 [PATCH v3 0/5] linux-user/riscv: add vector state to signal context Nicholas Piggin
2026-03-21 14:13 ` [PATCH v3 1/5] tests/tcg/riscv64: Add a user signal handling test Nicholas Piggin
2026-03-25 3:07 ` Alistair Francis
2026-03-21 14:13 ` [PATCH v3 2/5] linux-user/riscv: Allow restore_sigcontext to return error Nicholas Piggin
2026-03-25 3:07 ` Alistair Francis
2026-03-21 14:13 ` [PATCH v3 3/5] linux-user/riscv: Add extended state to sigcontext Nicholas Piggin
2026-03-25 3:14 ` Alistair Francis [this message]
2026-03-21 14:13 ` [PATCH v3 4/5] linux-user/riscv: Add vector state to signal context Nicholas Piggin
2026-03-25 3:45 ` Alistair Francis
2026-03-21 14:13 ` [PATCH v3 5/5] tests/tcg/riscv64: Add vector state to signal test Nicholas Piggin
2026-03-25 3:49 ` Alistair Francis
2026-03-25 4:45 ` [PATCH v3 0/5] linux-user/riscv: add vector state to signal context Alistair Francis
2026-03-26 6:22 ` Nicholas Piggin
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