From: Alistair Francis <alistair23@gmail.com>
To: Yifei Jiang <jiangyifei@huawei.com>
Cc: kvm-riscv@lists.infradead.org, Anup Patel <anup.patel@wdc.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"open list:Overall" <kvm@vger.kernel.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
libvir-list@redhat.com,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"Zhangxiaofeng \(F\)" <victor.zhangxiaofeng@huawei.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Zhanghailiang <zhang.zhanghailiang@huawei.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
yinyipeng <yinyipeng1@huawei.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
"Wubin \(H\)" <wu.wubin@huawei.com>,
"dengkai \(A\)" <dengkai1@huawei.com>
Subject: Re: [PATCH RFC v4 07/15] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
Date: Tue, 8 Dec 2020 14:29:47 -0800 [thread overview]
Message-ID: <CAKmqyKMXmCPyMmo_OHdeVZCjN1k_Lv9n_FVFe9pvbnoHhVSL1g@mail.gmail.com> (raw)
In-Reply-To: <20201203124703.168-8-jiangyifei@huawei.com>
On Thu, Dec 3, 2020 at 4:47 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Only support supervisor external interrupt currently.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> ---
> hw/intc/sifive_plic.c | 31 ++++++++++++++++++++++---------
> target/riscv/kvm.c | 19 +++++++++++++++++++
> target/riscv/kvm_riscv.h | 1 +
> 3 files changed, 42 insertions(+), 9 deletions(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index 97a1a27a9a..a419ca3a3c 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -31,6 +31,8 @@
> #include "target/riscv/cpu.h"
> #include "sysemu/sysemu.h"
> #include "migration/vmstate.h"
> +#include "sysemu/kvm.h"
> +#include "kvm_riscv.h"
>
> #define RISCV_DEBUG_PLIC 0
>
> @@ -147,15 +149,26 @@ static void sifive_plic_update(SiFivePLICState *plic)
> continue;
> }
> int level = sifive_plic_irqs_pending(plic, addrid);
> - switch (mode) {
> - case PLICMode_M:
> - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
> - break;
> - case PLICMode_S:
> - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
> - break;
> - default:
> - break;
> + if (kvm_enabled()) {
> + if (mode == PLICMode_M) {
> + continue;
> + }
> +#ifdef CONFIG_KVM
> + kvm_riscv_set_irq(RISCV_CPU(cpu), IRQ_S_EXT, level);
> +#endif
What if kvm_enalbed() is true, but CONFIG_KVM isn't defined?
Alistair
> + } else {
> + switch (mode) {
> + case PLICMode_M:
> + riscv_cpu_update_mip(RISCV_CPU(cpu),
> + MIP_MEIP, BOOL_TO_MASK(level));
> + break;
> + case PLICMode_S:
> + riscv_cpu_update_mip(RISCV_CPU(cpu),
> + MIP_SEIP, BOOL_TO_MASK(level));
> + break;
> + default:
> + break;
> + }
> }
> }
>
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 6250ca0c7d..b01ff0754c 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -454,3 +454,22 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> env->satp = 0;
> }
>
> +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
> +{
> + int ret;
> + unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET;
> +
> + if (irq != IRQ_S_EXT) {
> + return;
> + }
> +
> + if (!kvm_enabled()) {
> + return;
> + }
> +
> + ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
> + if (ret < 0) {
> + perror("Set irq failed");
> + abort();
> + }
> +}
> diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
> index f38c82bf59..ed281bdce0 100644
> --- a/target/riscv/kvm_riscv.h
> +++ b/target/riscv/kvm_riscv.h
> @@ -20,5 +20,6 @@
> #define QEMU_KVM_RISCV_H
>
> void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
> +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
>
> #endif
> --
> 2.19.1
>
>
next prev parent reply other threads:[~2020-12-08 22:38 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-03 12:46 [PATCH RFC v4 00/15] Add riscv kvm accel support Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 01/15] linux-header: Update linux/kvm.h Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 02/15] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 03/15] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2020-12-08 22:13 ` Alistair Francis
2020-12-03 12:46 ` [PATCH RFC v4 04/15] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 05/15] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 06/15] target/riscv: Support start kernel directly by KVM Yifei Jiang
2020-12-08 22:19 ` Alistair Francis
2020-12-15 7:19 ` Jiangyifei
2020-12-03 12:46 ` [PATCH RFC v4 07/15] hw/riscv: PLIC update external interrupt by KVM when kvm enabled Yifei Jiang
2020-12-08 22:29 ` Alistair Francis [this message]
2020-12-15 7:33 ` Jiangyifei
2020-12-03 12:46 ` [PATCH RFC v4 08/15] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 09/15] target/riscv: Add host cpu type Yifei Jiang
2020-12-08 22:21 ` Alistair Francis
2020-12-15 7:21 ` Jiangyifei
2020-12-03 12:46 ` [PATCH RFC v4 10/15] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang
2020-12-03 12:46 ` [PATCH RFC v4 11/15] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang
2020-12-03 12:47 ` [PATCH RFC v4 12/15] target/riscv: Support virtual time context synchronization Yifei Jiang
2020-12-03 12:47 ` [PATCH RFC v4 13/15] target/riscv: Introduce dynamic time frequency for virt machine Yifei Jiang
2020-12-08 22:25 ` Alistair Francis
2020-12-15 7:31 ` Jiangyifei
2021-01-05 17:36 ` Alistair Francis
2020-12-03 12:47 ` [PATCH RFC v4 14/15] target/riscv: Synchronize vcpu's frequency with KVM Yifei Jiang
2020-12-03 12:47 ` [PATCH RFC v4 15/15] target/riscv: Add time frequency migration support Yifei Jiang
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