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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::930; envelope-from=alistair23@gmail.com; helo=mail-ua1-x930.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, May 24, 2023 at 12:07=E2=80=AFAM Weiwei Li w= rote: > > pc_succ_insn is no longer useful after the introduce of cur_insn_len > and all pc related value use diff value instead of absolute value. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/translate.c | 7 +------ > 1 file changed, 1 insertion(+), 6 deletions(-) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 538187f93b..37d731f9c5 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -57,8 +57,6 @@ typedef enum { > > typedef struct DisasContext { > DisasContextBase base; > - /* pc_succ_insn points to the instruction following base.pc_next */ > - target_ulong pc_succ_insn; > target_ulong cur_insn_len; > target_ulong pc_save; > target_ulong priv_ver; > @@ -1147,7 +1145,6 @@ static void decode_opc(CPURISCVState *env, DisasCon= text *ctx, uint16_t opcode) > /* Check for compressed insn */ > if (ctx->cur_insn_len =3D=3D 2) { > ctx->opcode =3D opcode; > - ctx->pc_succ_insn =3D ctx->base.pc_next + 2; > /* > * The Zca extension is added as way to refer to instructions in= the C > * extension that do not include the floating-point loads and st= ores > @@ -1161,7 +1158,6 @@ static void decode_opc(CPURISCVState *env, DisasCon= text *ctx, uint16_t opcode) > translator_lduw(env, &ctx->base, > ctx->base.pc_next + 2)); > ctx->opcode =3D opcode32; > - ctx->pc_succ_insn =3D ctx->base.pc_next + 4; > > for (size_t i =3D 0; i < ARRAY_SIZE(decoders); ++i) { > if (decoders[i].guard_func(ctx) && > @@ -1182,7 +1178,6 @@ static void riscv_tr_init_disas_context(DisasContex= tBase *dcbase, CPUState *cs) > uint32_t tb_flags =3D ctx->base.tb->flags; > > ctx->pc_save =3D ctx->base.pc_first; > - ctx->pc_succ_insn =3D ctx->base.pc_first; > ctx->priv =3D FIELD_EX32(tb_flags, TB_FLAGS, PRIV); > ctx->mem_idx =3D FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); > ctx->mstatus_fs =3D FIELD_EX32(tb_flags, TB_FLAGS, FS); > @@ -1235,7 +1230,7 @@ static void riscv_tr_translate_insn(DisasContextBas= e *dcbase, CPUState *cpu) > > ctx->ol =3D ctx->xl; > decode_opc(env, ctx, opcode16); > - ctx->base.pc_next =3D ctx->pc_succ_insn; > + ctx->base.pc_next +=3D ctx->cur_insn_len; > > /* Only the first insn within a TB is allowed to cross a page bounda= ry. */ > if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { > -- > 2.25.1 > >