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From: Alistair Francis <alistair23@gmail.com>
Date: Thu, 26 Apr 2018 16:48:49 +0000
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Subject: Re: [Qemu-devel] [PATCH v8 10/35] RISC-V: Remove erroneous comment
 from translate.c
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To: Michael Clark <mjc@sifive.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, palmer@sifive.com, Alistair Francis <Alistair.Francis@wdc.com>, patches@groups.riscv.org

On Wed, Apr 25, 2018 at 5:00 PM Michael Clark <mjc@sifive.com> wrote:

> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>   target/riscv/translate.c | 1 -
>   1 file changed, 1 deletion(-)

> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 808eab7..c3a029a 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -280,7 +280,6 @@ static void gen_arith(DisasContext *ctx, uint32_t
opc, int rd, int rs1,
>           tcg_gen_andi_tl(source2, source2, 0x1F);
>           tcg_gen_sar_tl(source1, source1, source2);
>           break;
> -        /* fall through to SRA */
>   #endif
>       case OPC_RISC_SRA:
>           tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
> --
> 2.7.0