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Wed, 05 Mar 2025 20:21:40 -0800 (PST) MIME-Version: 1.0 References: <20250225005446.13894-1-sebastian.huber@embedded-brains.de> <20250225005446.13894-6-sebastian.huber@embedded-brains.de> In-Reply-To: <20250225005446.13894-6-sebastian.huber@embedded-brains.de> From: Alistair Francis Date: Thu, 6 Mar 2025 14:21:14 +1000 X-Gm-Features: AQ5f1Jpbd67JJpio6ETR3wX1PgFi8ge4-88Kzckd-BSOcd4OYCN0HtgcB13VvpY Message-ID: Subject: Re: [PATCH v2 5/6] hw/riscv: Configurable MPFS CLINT timebase freq To: Sebastian Huber Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Conor Dooley , Bin Meng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a33; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa33.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Feb 25, 2025 at 10:55=E2=80=AFAM Sebastian Huber wrote: > > This property enables the setting of the CLINT timebase frequency > through the command line, for example: > > -machine microchip-icicle-kit,clint-timebase-frequency=3D10000000 > > Signed-off-by: Sebastian Huber > Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/microchip_pfsoc.c | 49 +++++++++++++++++++++++++++--- > include/hw/riscv/microchip_pfsoc.h | 1 + > 2 files changed, 46 insertions(+), 4 deletions(-) > > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index df902c8667..9068eed780 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -39,6 +39,7 @@ > #include "qemu/units.h" > #include "qemu/cutils.h" > #include "qapi/error.h" > +#include "qapi/visitor.h" > #include "hw/boards.h" > #include "hw/loader.h" > #include "hw/sysbus.h" > @@ -61,9 +62,6 @@ > #define BIOS_FILENAME "hss.bin" > #define RESET_VECTOR 0x20220000 > > -/* CLINT timebase frequency */ > -#define CLINT_TIMEBASE_FREQ 1000000 > - > /* GEM version */ > #define GEM_REVISION 0x0107010c > > @@ -193,6 +191,7 @@ static void microchip_pfsoc_soc_instance_init(Object = *obj) > static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) > { > MachineState *ms =3D MACHINE(qdev_get_machine()); > + MicrochipIcicleKitState *iks =3D MICROCHIP_ICICLE_KIT_MACHINE(ms); > MicrochipPFSoCState *s =3D MICROCHIP_PFSOC(dev); > const MemMapEntry *memmap =3D microchip_pfsoc_memmap; > MemoryRegion *system_memory =3D get_system_memory(); > @@ -253,7 +252,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *= dev, Error **errp) > memmap[MICROCHIP_PFSOC_CLINT].base + RISCV_ACLINT_SWI_SIZE, > RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, > RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, > - CLINT_TIMEBASE_FREQ, false); > + iks->clint_timebase_freq, false); > > /* L2 cache controller */ > create_unimplemented_device("microchip.pfsoc.l2cc", > @@ -669,6 +668,40 @@ static void microchip_icicle_kit_machine_init(Machin= eState *machine) > } > } > > +static void microchip_icicle_kit_set_clint_timebase_freq(Object *obj, > + Visitor *v, > + const char *nam= e, > + void *opaque, > + Error **errp) > +{ > + MicrochipIcicleKitState *s =3D MICROCHIP_ICICLE_KIT_MACHINE(obj); > + uint32_t value; > + > + if (!visit_type_uint32(v, name, &value, errp)) { > + return; > + } > + > + s->clint_timebase_freq =3D value; > +} > + > +static void microchip_icicle_kit_get_clint_timebase_freq(Object *obj, > + Visitor *v, > + const char *nam= e, > + void *opaque, > + Error **errp) > +{ > + MicrochipIcicleKitState *s =3D MICROCHIP_ICICLE_KIT_MACHINE(obj); > + uint32_t value =3D s->clint_timebase_freq; > + > + visit_type_uint32(v, name, &value, errp); > +} > + > +static void microchip_icicle_kit_machine_instance_init(Object *obj) > +{ > + MicrochipIcicleKitState *m =3D MICROCHIP_ICICLE_KIT_MACHINE(obj); > + m->clint_timebase_freq =3D 1000000; > +} > + > static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, voi= d *data) > { > MachineClass *mc =3D MACHINE_CLASS(oc); > @@ -690,12 +723,20 @@ static void microchip_icicle_kit_machine_class_init= (ObjectClass *oc, void *data) > * See memory_tests() in mss_ddr.c in the HSS source code. > */ > mc->default_ram_size =3D 1537 * MiB; > + > + object_class_property_add(oc, "clint-timebase-frequency", "uint32_t"= , > + microchip_icicle_kit_get_clint_timebase_fr= eq, > + microchip_icicle_kit_set_clint_timebase_fr= eq, > + NULL, NULL); > + object_class_property_set_description(oc, "clint-timebase-frequency"= , > + "Set CLINT timebase frequency in Hz.")= ; > } > > static const TypeInfo microchip_icicle_kit_machine_typeinfo =3D { > .name =3D MACHINE_TYPE_NAME("microchip-icicle-kit"), > .parent =3D TYPE_MACHINE, > .class_init =3D microchip_icicle_kit_machine_class_init, > + .instance_init =3D microchip_icicle_kit_machine_instance_init, > .instance_size =3D sizeof(MicrochipIcicleKitState), > }; > > diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microc= hip_pfsoc.h > index daef086da6..7ca9b976c1 100644 > --- a/include/hw/riscv/microchip_pfsoc.h > +++ b/include/hw/riscv/microchip_pfsoc.h > @@ -67,6 +67,7 @@ typedef struct MicrochipIcicleKitState { > MachineState parent_obj; > > /*< public >*/ > + uint32_t clint_timebase_freq; > MicrochipPFSoCState soc; > } MicrochipIcicleKitState; > > -- > 2.43.0 >