* [PATCH v2 00/22] target/riscv: declarative CPU definitions
@ 2025-02-28 10:27 Paolo Bonzini
2025-02-28 10:27 ` [PATCH 01/22] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Paolo Bonzini
` (22 more replies)
0 siblings, 23 replies; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
As in v1, what I really wanted to achieve was removing RISC-V's
use of .instance_post_init; that's because RISC-V operate with an
opposite conception of .instance_post_init compared to everyone
else: RISC-V wants to register properties there, whereas x86 and
hw/pci-bridge/pcie_root_port.c want to set them. While it's possible
to move RISC-V's code to instance_init, the others have to run after
global properties have been set by device_post_init().
The way to get there is to make CPU definitions entirely declarative.
Previously, multiple instance_init functions each override the properties
that were set by the superclass, and the code used a mix of subclassing
and direct invocation of other functions. Now, instead, after .class_init
all the settings for each model are available in a RISCVCPUDef struct,
and the result is copied into the RISCVCPU at .instance_init time.
This is done with a single function that starts from the parent's
RISCVCPUDef and applies the delta stored in the CPU's class_data.
Apart from the small reduction in line count, one advantage is that
more validation of the models can be done unconditionally at startup,
instead of happening dynamically if a CPU model is chosen.
Based-on: <20250218165757.554178-1-pbonzini@redhat.com>
Paolo
v1->v2:
- merged "remove target/riscv: remove unused macro DEFINE_CPU"
- max SATP mode refactoring moved to its own series
- included a couple of Philippe's patches from his "const class_data" series
- RISCVCPUDef initializers all declared as const
Paolo Bonzini (20):
target/riscv: introduce RISCVCPUDef
target/riscv: store RISCVCPUDef struct directly in the class
target/riscv: merge riscv_cpu_class_init with the class_base function
target/riscv: move RISCVCPUConfig fields to a header file
target/riscv: add more RISCVCPUDef fields
target/riscv: convert abstract CPU classes to RISCVCPUDef
target/riscv: do not make RISCVCPUConfig fields conditional
target/riscv: convert profile CPU models to RISCVCPUDef
target/riscv: convert bare CPU models to RISCVCPUDef
target/riscv: convert dynamic CPU models to RISCVCPUDef
target/riscv: convert SiFive E CPU models to RISCVCPUDef
target/riscv: convert ibex CPU models to RISCVCPUDef
target/riscv: convert SiFive U models to RISCVCPUDef
target/riscv: th: make CSR insertion test a bit more intuitive
target/riscv: generalize custom CSR functionality
target/riscv: convert TT C906 to RISCVCPUDef
target/riscv: convert TT Ascalon to RISCVCPUDef
target/riscv: convert Ventana V1 to RISCVCPUDef
target/riscv: convert Xiangshan Nanhu to RISCVCPUDef
target/riscv: remove .instance_post_init
Philippe Mathieu-Daudé (2):
target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL
target/riscv: Convert misa_mxl_max using GLib macros
target/riscv/cpu-qom.h | 2 +
target/riscv/cpu.h | 27 +-
target/riscv/cpu_cfg.h | 160 +-----
target/riscv/cpu_cfg_fields.h.inc | 165 ++++++
hw/riscv/boot.c | 2 +-
target/riscv/cpu.c | 909 ++++++++++++++----------------
target/riscv/csr.c | 2 +-
target/riscv/gdbstub.c | 6 +-
target/riscv/kvm/kvm-cpu.c | 23 +-
target/riscv/machine.c | 6 +-
target/riscv/tcg/tcg-cpu.c | 10 +-
target/riscv/th_csr.c | 30 +-
target/riscv/translate.c | 2 +-
13 files changed, 632 insertions(+), 712 deletions(-)
create mode 100644 target/riscv/cpu_cfg_fields.h.inc
--
2.48.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 01/22] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-03-06 0:46 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 02/22] target/riscv: Convert misa_mxl_max using GLib macros Paolo Bonzini
` (21 subsequent siblings)
22 siblings, 1 reply; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel
Cc: alistair.francis, Philippe Mathieu-Daudé, Richard Henderson
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Link: https://lore.kernel.org/r/20250212213249.45574-7-philmd@linaro.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index df7a05e7d15..3041a4be5c9 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -543,7 +543,7 @@ struct RISCVCPUClass {
DeviceRealize parent_realize;
ResettablePhases parent_phases;
- uint32_t misa_mxl_max; /* max mxl for this cpu */
+ RISCVMXL misa_mxl_max; /* max mxl for this cpu */
};
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 244e44ce410..85dc2fe3bec 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2961,7 +2961,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
- mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
+ mcc->misa_mxl_max = (RISCVMXL)(uintptr_t)data;
riscv_cpu_validate_misa_mxl(mcc);
}
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 02/22] target/riscv: Convert misa_mxl_max using GLib macros
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
2025-02-28 10:27 ` [PATCH 01/22] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-03-06 0:47 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 03/22] target/riscv: introduce RISCVCPUDef Paolo Bonzini
` (20 subsequent siblings)
22 siblings, 1 reply; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel
Cc: alistair.francis, Philippe Mathieu-Daudé, Richard Henderson
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Use GLib conversion macros to pass misa_mxl_max as
riscv_cpu_class_init() class data.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Link: https://lore.kernel.org/r/20250212213249.45574-8-philmd@linaro.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 85dc2fe3bec..f05b72ac873 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2961,7 +2961,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
- mcc->misa_mxl_max = (RISCVMXL)(uintptr_t)data;
+ mcc->misa_mxl_max = (RISCVMXL)GPOINTER_TO_UINT(data);
riscv_cpu_validate_misa_mxl(mcc);
}
@@ -3063,7 +3063,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.parent = TYPE_RISCV_DYNAMIC_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
- .class_data = (void *)(misa_mxl_max) \
+ .class_data = GUINT_TO_POINTER(misa_mxl_max) \
}
#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \
@@ -3072,7 +3072,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.parent = TYPE_RISCV_VENDOR_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
- .class_data = (void *)(misa_mxl_max) \
+ .class_data = GUINT_TO_POINTER(misa_mxl_max) \
}
#define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \
@@ -3081,7 +3081,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.parent = TYPE_RISCV_BARE_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
- .class_data = (void *)(misa_mxl_max) \
+ .class_data = GUINT_TO_POINTER(misa_mxl_max) \
}
#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \
@@ -3090,7 +3090,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.parent = TYPE_RISCV_BARE_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
- .class_data = (void *)(misa_mxl_max) \
+ .class_data = GUINT_TO_POINTER(misa_mxl_max) \
}
static const TypeInfo riscv_cpu_type_infos[] = {
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 03/22] target/riscv: introduce RISCVCPUDef
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
2025-02-28 10:27 ` [PATCH 01/22] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Paolo Bonzini
2025-02-28 10:27 ` [PATCH 02/22] target/riscv: Convert misa_mxl_max using GLib macros Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-02-28 17:19 ` Richard Henderson
2025-02-28 10:27 ` [PATCH 04/22] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
` (19 subsequent siblings)
22 siblings, 1 reply; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
Start putting all the CPU definitions in a struct. Later this will replace
instance_init functions with declarative code, for now just remove the
ugly cast of class_data.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.h | 4 ++++
target/riscv/cpu.c | 27 ++++++++++++++++++---------
2 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3041a4be5c9..743afeb1655 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -531,6 +531,10 @@ struct ArchCPU {
const GPtrArray *decoders;
};
+typedef struct RISCVCPUDef {
+ RISCVMXL misa_mxl_max; /* max mxl for this cpu */
+} RISCVCPUDef;
+
/**
* RISCVCPUClass:
* @parent_realize: The parent class' realize handler.
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f05b72ac873..a71d806e35f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2960,8 +2960,9 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data)
static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
+ const RISCVCPUDef *def = data;
- mcc->misa_mxl_max = (RISCVMXL)GPOINTER_TO_UINT(data);
+ mcc->misa_mxl_max = def->misa_mxl_max;
riscv_cpu_validate_misa_mxl(mcc);
}
@@ -3057,40 +3058,48 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
}
#endif
-#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \
+#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max_, initfn) \
{ \
.name = (type_name), \
.parent = TYPE_RISCV_DYNAMIC_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
- .class_data = GUINT_TO_POINTER(misa_mxl_max) \
+ .class_data = (void*) &((const RISCVCPUDef) { \
+ .misa_mxl_max = (misa_mxl_max_), \
+ }), \
}
-#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \
+#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max_, initfn) \
{ \
.name = (type_name), \
.parent = TYPE_RISCV_VENDOR_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
- .class_data = GUINT_TO_POINTER(misa_mxl_max) \
+ .class_data = (void*) &((const RISCVCPUDef) { \
+ .misa_mxl_max = (misa_mxl_max_), \
+ }), \
}
-#define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \
+#define DEFINE_BARE_CPU(type_name, misa_mxl_max_, initfn) \
{ \
.name = (type_name), \
.parent = TYPE_RISCV_BARE_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
- .class_data = GUINT_TO_POINTER(misa_mxl_max) \
+ .class_data = (void*) &((const RISCVCPUDef) { \
+ .misa_mxl_max = (misa_mxl_max_), \
+ }), \
}
-#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \
+#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max_, initfn) \
{ \
.name = (type_name), \
.parent = TYPE_RISCV_BARE_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
- .class_data = GUINT_TO_POINTER(misa_mxl_max) \
+ .class_data = (void*) &((const RISCVCPUDef) { \
+ .misa_mxl_max = (misa_mxl_max_), \
+ }), \
}
static const TypeInfo riscv_cpu_type_infos[] = {
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 04/22] target/riscv: store RISCVCPUDef struct directly in the class
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (2 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 03/22] target/riscv: introduce RISCVCPUDef Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-03-06 0:50 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 05/22] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
` (18 subsequent siblings)
22 siblings, 1 reply; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
Prepare for adding more fields to RISCVCPUDef and reading them in
riscv_cpu_init: instead of storing the misa_mxl_max field in
RISCVCPUClass, ensure that there's always a valid RISCVCPUDef struct
and go through it.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.h | 2 +-
hw/riscv/boot.c | 2 +-
target/riscv/cpu.c | 23 ++++++++++++++++++-----
target/riscv/gdbstub.c | 6 +++---
target/riscv/kvm/kvm-cpu.c | 21 +++++++++------------
target/riscv/machine.c | 6 +++---
target/riscv/tcg/tcg-cpu.c | 10 +++++-----
target/riscv/translate.c | 2 +-
8 files changed, 41 insertions(+), 31 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 743afeb1655..a038122f80c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -547,7 +547,7 @@ struct RISCVCPUClass {
DeviceRealize parent_realize;
ResettablePhases parent_phases;
- RISCVMXL misa_mxl_max; /* max mxl for this cpu */
+ RISCVCPUDef *def;
};
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index c309441b7d8..13728e137c4 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -37,7 +37,7 @@
bool riscv_is_32bit(RISCVHartArrayState *harts)
{
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]);
- return mcc->misa_mxl_max == MXL_RV32;
+ return mcc->def->misa_mxl_max == MXL_RV32;
}
/*
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a71d806e35f..51acce07752 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -354,7 +354,7 @@ void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)
int riscv_cpu_max_xlen(RISCVCPUClass *mcc)
{
- return 16 << mcc->misa_mxl_max;
+ return 16 << mcc->def->misa_mxl_max;
}
#ifndef CONFIG_USER_ONLY
@@ -1054,7 +1054,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
mcc->parent_phases.hold(obj, type);
}
#ifndef CONFIG_USER_ONLY
- env->misa_mxl = mcc->misa_mxl_max;
+ env->misa_mxl = mcc->def->misa_mxl_max;
env->priv = PRV_M;
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
if (env->misa_mxl > MXL_RV32) {
@@ -1447,7 +1447,7 @@ static void riscv_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env;
- env->misa_mxl = mcc->misa_mxl_max;
+ env->misa_mxl = mcc->def->misa_mxl_max;
#ifndef CONFIG_USER_ONLY
qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
@@ -1544,7 +1544,7 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
CPUClass *cc = CPU_CLASS(mcc);
/* Validate that MISA_MXL is set properly. */
- switch (mcc->misa_mxl_max) {
+ switch (mcc->def->misa_mxl_max) {
#ifdef TARGET_RISCV64
case MXL_RV64:
case MXL_RV128:
@@ -2957,12 +2957,24 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data)
device_class_set_props(dc, riscv_cpu_properties);
}
+static void riscv_cpu_class_base_init(ObjectClass *c, void *data)
+{
+ RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
+ RISCVCPUClass *pcc = RISCV_CPU_CLASS(object_class_get_parent(c));
+
+ if (pcc->def) {
+ mcc->def = g_memdup2(pcc->def, sizeof(*pcc->def));
+ } else {
+ mcc->def = g_new0(RISCVCPUDef, 1);
+ }
+}
+
static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
const RISCVCPUDef *def = data;
- mcc->misa_mxl_max = def->misa_mxl_max;
+ mcc->def->misa_mxl_max = def->misa_mxl_max;
riscv_cpu_validate_misa_mxl(mcc);
}
@@ -3113,6 +3125,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.abstract = true,
.class_size = sizeof(RISCVCPUClass),
.class_init = riscv_cpu_common_class_init,
+ .class_base_init = riscv_cpu_class_base_init,
},
{
.name = TYPE_RISCV_DYNAMIC_CPU,
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 18e88f416af..1934f919c01 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -62,7 +62,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
- switch (mcc->misa_mxl_max) {
+ switch (mcc->def->misa_mxl_max) {
case MXL_RV32:
return gdb_get_reg32(mem_buf, tmp);
case MXL_RV64:
@@ -82,7 +82,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
int length = 0;
target_ulong tmp;
- switch (mcc->misa_mxl_max) {
+ switch (mcc->def->misa_mxl_max) {
case MXL_RV32:
tmp = (int32_t)ldl_p(mem_buf);
length = 4;
@@ -359,7 +359,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
0);
}
- switch (mcc->misa_mxl_max) {
+ switch (mcc->def->misa_mxl_max) {
case MXL_RV32:
gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
riscv_gdb_set_virtual,
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 23ce7793594..f3ec4f33931 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -1985,22 +1985,19 @@ static void kvm_cpu_accel_register_types(void)
}
type_init(kvm_cpu_accel_register_types);
-static void riscv_host_cpu_class_init(ObjectClass *c, void *data)
-{
- RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
-
-#if defined(TARGET_RISCV32)
- mcc->misa_mxl_max = MXL_RV32;
-#elif defined(TARGET_RISCV64)
- mcc->misa_mxl_max = MXL_RV64;
-#endif
-}
-
static const TypeInfo riscv_kvm_cpu_type_infos[] = {
{
.name = TYPE_RISCV_CPU_HOST,
.parent = TYPE_RISCV_CPU,
- .class_init = riscv_host_cpu_class_init,
+#if defined(TARGET_RISCV32)
+ .class_data = &((const RISCVCPUDef) {
+ .misa_mxl_max = MXL_RV32,
+ },
+#elif defined(TARGET_RISCV64)
+ .class_data = &((const RISCVCPUDef) {
+ .misa_mxl_max = MXL_RV64,
+ },
+#endif
}
};
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index c3d8e7c4005..98d20afd04d 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -170,7 +170,7 @@ static bool rv128_needed(void *opaque)
{
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(opaque);
- return mcc->misa_mxl_max == MXL_RV128;
+ return mcc->def->misa_mxl_max == MXL_RV128;
}
static const VMStateDescription vmstate_rv128 = {
@@ -383,8 +383,8 @@ static bool riscv_validate_misa_mxl(void *opaque, int version_id)
uint32_t misa_mxl_saved = env->misa_mxl;
/* Preserve misa_mxl even if the migration stream corrupted it */
- env->misa_mxl = mcc->misa_mxl_max;
- return misa_mxl_saved == mcc->misa_mxl_max;
+ env->misa_mxl = mcc->def->misa_mxl_max;
+ return misa_mxl_saved == mcc->def->misa_mxl_max;
}
const VMStateDescription vmstate_riscv_cpu = {
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index e5e01715f10..f434b2448db 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -579,7 +579,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
+ if (mcc->def->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
error_setg(errp, "Zcf extension is only relevant to RV32");
return;
}
@@ -676,7 +676,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (mcc->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) {
+ if (mcc->def->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) {
error_setg(errp, "svukte is not supported for RV32");
return;
}
@@ -891,7 +891,7 @@ static void cpu_enable_zc_implied_rules(RISCVCPU *cpu)
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
- if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
+ if (riscv_has_ext(env, RVF) && mcc->def->misa_mxl_max == MXL_RV32) {
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
}
}
@@ -900,7 +900,7 @@ static void cpu_enable_zc_implied_rules(RISCVCPU *cpu)
if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
- if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
+ if (riscv_has_ext(env, RVF) && mcc->def->misa_mxl_max == MXL_RV32) {
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
}
@@ -1024,7 +1024,7 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
return false;
}
- if (mcc->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
+ if (mcc->def->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
/* Missing 128-bit aligned atomics */
error_setg(errp,
"128-bit RISC-V currently does not work with Multi "
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 698b74f7a8f..782e724a648 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1234,7 +1234,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;
ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
- ctx->misa_mxl_max = mcc->misa_mxl_max;
+ ctx->misa_mxl_max = mcc->def->misa_mxl_max;
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
ctx->cs = cs;
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 05/22] target/riscv: merge riscv_cpu_class_init with the class_base function
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (3 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 04/22] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-03-06 0:52 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 06/22] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
` (17 subsequent siblings)
22 siblings, 1 reply; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
Since all TYPE_RISCV_CPU subclasses support a class_data of type
RISCVCPUDef, process it even before calling the .class_init function
for the subclasses.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 21 ++++++++++-----------
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 51acce07752..91dd63edc9f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2967,15 +2967,18 @@ static void riscv_cpu_class_base_init(ObjectClass *c, void *data)
} else {
mcc->def = g_new0(RISCVCPUDef, 1);
}
-}
-static void riscv_cpu_class_init(ObjectClass *c, void *data)
-{
- RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
- const RISCVCPUDef *def = data;
+ if (data) {
+ const RISCVCPUDef *def = data;
+ if (def->misa_mxl_max) {
+ assert(def->misa_mxl_max <= MXL_RV128);
+ mcc->def->misa_mxl_max = def->misa_mxl_max;
+ }
+ }
- mcc->def->misa_mxl_max = def->misa_mxl_max;
- riscv_cpu_validate_misa_mxl(mcc);
+ if (!object_class_is_abstract(c)) {
+ riscv_cpu_validate_misa_mxl(mcc);
+ }
}
static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
@@ -3075,7 +3078,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.name = (type_name), \
.parent = TYPE_RISCV_DYNAMIC_CPU, \
.instance_init = (initfn), \
- .class_init = riscv_cpu_class_init, \
.class_data = (void*) &((const RISCVCPUDef) { \
.misa_mxl_max = (misa_mxl_max_), \
}), \
@@ -3086,7 +3088,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.name = (type_name), \
.parent = TYPE_RISCV_VENDOR_CPU, \
.instance_init = (initfn), \
- .class_init = riscv_cpu_class_init, \
.class_data = (void*) &((const RISCVCPUDef) { \
.misa_mxl_max = (misa_mxl_max_), \
}), \
@@ -3097,7 +3098,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.name = (type_name), \
.parent = TYPE_RISCV_BARE_CPU, \
.instance_init = (initfn), \
- .class_init = riscv_cpu_class_init, \
.class_data = (void*) &((const RISCVCPUDef) { \
.misa_mxl_max = (misa_mxl_max_), \
}), \
@@ -3108,7 +3108,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.name = (type_name), \
.parent = TYPE_RISCV_BARE_CPU, \
.instance_init = (initfn), \
- .class_init = riscv_cpu_class_init, \
.class_data = (void*) &((const RISCVCPUDef) { \
.misa_mxl_max = (misa_mxl_max_), \
}), \
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 06/22] target/riscv: move RISCVCPUConfig fields to a header file
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (4 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 05/22] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-03-06 0:53 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 07/22] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
` (16 subsequent siblings)
22 siblings, 1 reply; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
To support merging a subclass's RISCVCPUDef into the superclass, a list
of all the CPU features is needed. Put them into a header file that
can be included multiple times, expanding the macros BOOL_FIELD and
TYPE_FIELD to different operations.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu_cfg.h | 160 +---------------------------
target/riscv/cpu_cfg_fields.h.inc | 167 ++++++++++++++++++++++++++++++
2 files changed, 170 insertions(+), 157 deletions(-)
create mode 100644 target/riscv/cpu_cfg_fields.h.inc
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 7b7067d5bee..e9bf75730a6 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -22,163 +22,9 @@
#define RISCV_CPU_CFG_H
struct RISCVCPUConfig {
- bool ext_zba;
- bool ext_zbb;
- bool ext_zbc;
- bool ext_zbkb;
- bool ext_zbkc;
- bool ext_zbkx;
- bool ext_zbs;
- bool ext_zca;
- bool ext_zcb;
- bool ext_zcd;
- bool ext_zce;
- bool ext_zcf;
- bool ext_zcmp;
- bool ext_zcmt;
- bool ext_zk;
- bool ext_zkn;
- bool ext_zknd;
- bool ext_zkne;
- bool ext_zknh;
- bool ext_zkr;
- bool ext_zks;
- bool ext_zksed;
- bool ext_zksh;
- bool ext_zkt;
- bool ext_zifencei;
- bool ext_zicntr;
- bool ext_zicsr;
- bool ext_zicbom;
- bool ext_zicbop;
- bool ext_zicboz;
- bool ext_zicfilp;
- bool ext_zicfiss;
- bool ext_zicond;
- bool ext_zihintntl;
- bool ext_zihintpause;
- bool ext_zihpm;
- bool ext_zimop;
- bool ext_zcmop;
- bool ext_ztso;
- bool ext_smstateen;
- bool ext_sstc;
- bool ext_smcdeleg;
- bool ext_ssccfg;
- bool ext_smcntrpmf;
- bool ext_smcsrind;
- bool ext_sscsrind;
- bool ext_ssdbltrp;
- bool ext_smdbltrp;
- bool ext_svadu;
- bool ext_svinval;
- bool ext_svnapot;
- bool ext_svpbmt;
- bool ext_svvptc;
- bool ext_svukte;
- bool ext_zdinx;
- bool ext_zaamo;
- bool ext_zacas;
- bool ext_zama16b;
- bool ext_zabha;
- bool ext_zalrsc;
- bool ext_zawrs;
- bool ext_zfa;
- bool ext_zfbfmin;
- bool ext_zfh;
- bool ext_zfhmin;
- bool ext_zfinx;
- bool ext_zhinx;
- bool ext_zhinxmin;
- bool ext_zve32f;
- bool ext_zve32x;
- bool ext_zve64f;
- bool ext_zve64d;
- bool ext_zve64x;
- bool ext_zvbb;
- bool ext_zvbc;
- bool ext_zvkb;
- bool ext_zvkg;
- bool ext_zvkned;
- bool ext_zvknha;
- bool ext_zvknhb;
- bool ext_zvksed;
- bool ext_zvksh;
- bool ext_zvkt;
- bool ext_zvkn;
- bool ext_zvknc;
- bool ext_zvkng;
- bool ext_zvks;
- bool ext_zvksc;
- bool ext_zvksg;
- bool ext_zmmul;
- bool ext_zvfbfmin;
- bool ext_zvfbfwma;
- bool ext_zvfh;
- bool ext_zvfhmin;
- bool ext_smaia;
- bool ext_ssaia;
- bool ext_sscofpmf;
- bool ext_smepmp;
- bool ext_smrnmi;
- bool ext_ssnpm;
- bool ext_smnpm;
- bool ext_smmpm;
- bool ext_sspm;
- bool ext_supm;
- bool rvv_ta_all_1s;
- bool rvv_ma_all_1s;
- bool rvv_vl_half_avl;
-
- uint32_t mvendorid;
- uint64_t marchid;
- uint64_t mimpid;
-
- /* Named features */
- bool ext_svade;
- bool ext_zic64b;
- bool ext_ssstateen;
- bool ext_sha;
-
- /*
- * Always 'true' booleans for named features
- * TCG always implement/can't be user disabled,
- * based on spec version.
- */
- bool has_priv_1_13;
- bool has_priv_1_12;
- bool has_priv_1_11;
-
- /* Vendor-specific custom extensions */
- bool ext_xtheadba;
- bool ext_xtheadbb;
- bool ext_xtheadbs;
- bool ext_xtheadcmo;
- bool ext_xtheadcondmov;
- bool ext_xtheadfmemidx;
- bool ext_xtheadfmv;
- bool ext_xtheadmac;
- bool ext_xtheadmemidx;
- bool ext_xtheadmempair;
- bool ext_xtheadsync;
- bool ext_XVentanaCondOps;
-
- uint32_t pmu_mask;
- uint16_t vlenb;
- uint16_t elen;
- uint16_t cbom_blocksize;
- uint16_t cbop_blocksize;
- uint16_t cboz_blocksize;
- bool mmu;
- bool pmp;
- bool debug;
- bool misa_w;
-
- bool short_isa_string;
-
-#ifndef CONFIG_USER_ONLY
- int8_t max_satp_mode;
-#endif
+#define BOOL_FIELD(x) bool x;
+#define TYPED_FIELD(type, x) type x;
+#include "cpu_cfg_fields.h.inc"
};
typedef struct RISCVCPUConfig RISCVCPUConfig;
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
new file mode 100644
index 00000000000..a42f298017f
--- /dev/null
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -0,0 +1,167 @@
+/*
+ * Required definitions before including this file:
+ *
+ * #define BOOL_FIELD(x)
+ * #define TYPED_FIELD(type, x)
+ */
+
+BOOL_FIELD(ext_zba)
+BOOL_FIELD(ext_zbb)
+BOOL_FIELD(ext_zbc)
+BOOL_FIELD(ext_zbkb)
+BOOL_FIELD(ext_zbkc)
+BOOL_FIELD(ext_zbkx)
+BOOL_FIELD(ext_zbs)
+BOOL_FIELD(ext_zca)
+BOOL_FIELD(ext_zcb)
+BOOL_FIELD(ext_zcd)
+BOOL_FIELD(ext_zce)
+BOOL_FIELD(ext_zcf)
+BOOL_FIELD(ext_zcmp)
+BOOL_FIELD(ext_zcmt)
+BOOL_FIELD(ext_zk)
+BOOL_FIELD(ext_zkn)
+BOOL_FIELD(ext_zknd)
+BOOL_FIELD(ext_zkne)
+BOOL_FIELD(ext_zknh)
+BOOL_FIELD(ext_zkr)
+BOOL_FIELD(ext_zks)
+BOOL_FIELD(ext_zksed)
+BOOL_FIELD(ext_zksh)
+BOOL_FIELD(ext_zkt)
+BOOL_FIELD(ext_zifencei)
+BOOL_FIELD(ext_zicntr)
+BOOL_FIELD(ext_zicsr)
+BOOL_FIELD(ext_zicbom)
+BOOL_FIELD(ext_zicbop)
+BOOL_FIELD(ext_zicboz)
+BOOL_FIELD(ext_zicfilp)
+BOOL_FIELD(ext_zicfiss)
+BOOL_FIELD(ext_zicond)
+BOOL_FIELD(ext_zihintntl)
+BOOL_FIELD(ext_zihintpause)
+BOOL_FIELD(ext_zihpm)
+BOOL_FIELD(ext_zimop)
+BOOL_FIELD(ext_zcmop)
+BOOL_FIELD(ext_ztso)
+BOOL_FIELD(ext_smstateen)
+BOOL_FIELD(ext_sstc)
+BOOL_FIELD(ext_smcdeleg)
+BOOL_FIELD(ext_ssccfg)
+BOOL_FIELD(ext_smcntrpmf)
+BOOL_FIELD(ext_smcsrind)
+BOOL_FIELD(ext_sscsrind)
+BOOL_FIELD(ext_ssdbltrp)
+BOOL_FIELD(ext_smdbltrp)
+BOOL_FIELD(ext_svadu)
+BOOL_FIELD(ext_svinval)
+BOOL_FIELD(ext_svnapot)
+BOOL_FIELD(ext_svpbmt)
+BOOL_FIELD(ext_svvptc)
+BOOL_FIELD(ext_svukte)
+BOOL_FIELD(ext_zdinx)
+BOOL_FIELD(ext_zaamo)
+BOOL_FIELD(ext_zacas)
+BOOL_FIELD(ext_zama16b)
+BOOL_FIELD(ext_zabha)
+BOOL_FIELD(ext_zalrsc)
+BOOL_FIELD(ext_zawrs)
+BOOL_FIELD(ext_zfa)
+BOOL_FIELD(ext_zfbfmin)
+BOOL_FIELD(ext_zfh)
+BOOL_FIELD(ext_zfhmin)
+BOOL_FIELD(ext_zfinx)
+BOOL_FIELD(ext_zhinx)
+BOOL_FIELD(ext_zhinxmin)
+BOOL_FIELD(ext_zve32f)
+BOOL_FIELD(ext_zve32x)
+BOOL_FIELD(ext_zve64f)
+BOOL_FIELD(ext_zve64d)
+BOOL_FIELD(ext_zve64x)
+BOOL_FIELD(ext_zvbb)
+BOOL_FIELD(ext_zvbc)
+BOOL_FIELD(ext_zvkb)
+BOOL_FIELD(ext_zvkg)
+BOOL_FIELD(ext_zvkned)
+BOOL_FIELD(ext_zvknha)
+BOOL_FIELD(ext_zvknhb)
+BOOL_FIELD(ext_zvksed)
+BOOL_FIELD(ext_zvksh)
+BOOL_FIELD(ext_zvkt)
+BOOL_FIELD(ext_zvkn)
+BOOL_FIELD(ext_zvknc)
+BOOL_FIELD(ext_zvkng)
+BOOL_FIELD(ext_zvks)
+BOOL_FIELD(ext_zvksc)
+BOOL_FIELD(ext_zvksg)
+BOOL_FIELD(ext_zmmul)
+BOOL_FIELD(ext_zvfbfmin)
+BOOL_FIELD(ext_zvfbfwma)
+BOOL_FIELD(ext_zvfh)
+BOOL_FIELD(ext_zvfhmin)
+BOOL_FIELD(ext_smaia)
+BOOL_FIELD(ext_ssaia)
+BOOL_FIELD(ext_sscofpmf)
+BOOL_FIELD(ext_smepmp)
+BOOL_FIELD(ext_smrnmi)
+BOOL_FIELD(ext_ssnpm)
+BOOL_FIELD(ext_smnpm)
+BOOL_FIELD(ext_smmpm)
+BOOL_FIELD(ext_sspm)
+BOOL_FIELD(ext_supm)
+BOOL_FIELD(rvv_ta_all_1s)
+BOOL_FIELD(rvv_ma_all_1s)
+BOOL_FIELD(rvv_vl_half_avl)
+/* Named features */
+BOOL_FIELD(ext_svade)
+BOOL_FIELD(ext_zic64b)
+BOOL_FIELD(ext_ssstateen)
+BOOL_FIELD(ext_sha)
+
+/*
+ * Always 'true' booleans for named features
+ * TCG always implement/can't be user disabled,
+ * based on spec version.
+ */
+BOOL_FIELD(has_priv_1_13)
+BOOL_FIELD(has_priv_1_12)
+BOOL_FIELD(has_priv_1_11)
+
+/* Vendor-specific custom extensions */
+BOOL_FIELD(ext_xtheadba)
+BOOL_FIELD(ext_xtheadbb)
+BOOL_FIELD(ext_xtheadbs)
+BOOL_FIELD(ext_xtheadcmo)
+BOOL_FIELD(ext_xtheadcondmov)
+BOOL_FIELD(ext_xtheadfmemidx)
+BOOL_FIELD(ext_xtheadfmv)
+BOOL_FIELD(ext_xtheadmac)
+BOOL_FIELD(ext_xtheadmemidx)
+BOOL_FIELD(ext_xtheadmempair)
+BOOL_FIELD(ext_xtheadsync)
+BOOL_FIELD(ext_XVentanaCondOps)
+
+BOOL_FIELD(mmu)
+BOOL_FIELD(pmp)
+BOOL_FIELD(debug)
+BOOL_FIELD(misa_w)
+
+BOOL_FIELD(short_isa_string)
+
+TYPED_FIELD(uint32_t, mvendorid)
+TYPED_FIELD(uint64_t, marchid)
+TYPED_FIELD(uint64_t, mimpid)
+
+TYPED_FIELD(uint32_t, pmu_mask)
+TYPED_FIELD(uint16_t, vlenb)
+TYPED_FIELD(uint16_t, elen)
+TYPED_FIELD(uint16_t, cbom_blocksize)
+TYPED_FIELD(uint16_t, cbop_blocksize)
+TYPED_FIELD(uint16_t, cboz_blocksize)
+
+#ifndef CONFIG_USER_ONLY
+TYPED_FIELD(int8_t, max_satp_mode)
+#endif
+
+#undef BOOL_FIELD
+#undef TYPED_FIELD
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 07/22] target/riscv: add more RISCVCPUDef fields
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (5 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 06/22] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-02-28 10:27 ` [PATCH 08/22] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
` (15 subsequent siblings)
22 siblings, 0 replies; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
Allow using RISCVCPUDef to replicate all the logic of custom .instance_init
functions. To simulate inheritance, merge the child's RISCVCPUDef with
the parent and then finally move it to the CPUState at the end of
TYPE_RISCV_CPU's own instance_init function.
STRUCT_FIELD is introduced here because I am not sure it is needed;
it is a bit ugly and I wanted not to have it in the patch that
introduces cpu_cfg_fields.h.inc. I don't really understand why satp_mode
is included in RISCVCPUConfig; therefore, the end of the series includes
a patch to move satp_mode directly in RISCVCPU, thus removing the need
for STRUCT_FIELD; it can be moved before this one in a non-RFC posting.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.h | 4 ++++
target/riscv/cpu.c | 30 +++++++++++++++++++++++++++++-
target/riscv/kvm/kvm-cpu.c | 2 ++
3 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a038122f80c..8c9e73c68cc 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -533,6 +533,10 @@ struct ArchCPU {
typedef struct RISCVCPUDef {
RISCVMXL misa_mxl_max; /* max mxl for this cpu */
+ uint32_t misa_ext;
+ int priv_spec;
+ int32_t vext_spec;
+ RISCVCPUConfig cfg;
} RISCVCPUDef;
/**
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 91dd63edc9f..c513d7ce32d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -74,6 +74,13 @@ bool riscv_cpu_option_set(const char *optname)
return g_hash_table_contains(general_user_opts, optname);
}
+static void riscv_cpu_cfg_merge(RISCVCPUConfig *dest, const RISCVCPUConfig *src)
+{
+#define BOOL_FIELD(x) dest->x |= src->x;
+#define TYPED_FIELD(type, x) if (src->x) dest->x = src->x;
+#include "cpu_cfg_fields.h.inc"
+}
+
#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
{#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
@@ -432,7 +439,7 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit)
}
static void set_satp_mode_max_supported(RISCVCPU *cpu,
- uint8_t satp_mode)
+ int satp_mode)
{
bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
@@ -1480,6 +1487,16 @@ static void riscv_cpu_init(Object *obj)
#ifndef CONFIG_USER_ONLY
cpu->cfg.max_satp_mode = -1;
#endif /* CONFIG_USER_ONLY */
+
+ env->misa_ext_mask = env->misa_ext = mcc->def->misa_ext;
+ riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg);
+
+ if (mcc->def->priv_spec != RISCV_PROFILE_ATTR_UNUSED) {
+ cpu->env.priv_ver = mcc->def->priv_spec;
+ }
+ if (mcc->def->vext_spec != RISCV_PROFILE_ATTR_UNUSED) {
+ cpu->env.vext_ver = mcc->def->vext_spec;
+ }
}
static void riscv_bare_cpu_init(Object *obj)
@@ -2974,6 +2991,17 @@ static void riscv_cpu_class_base_init(ObjectClass *c, void *data)
assert(def->misa_mxl_max <= MXL_RV128);
mcc->def->misa_mxl_max = def->misa_mxl_max;
}
+ if (def->priv_spec != RISCV_PROFILE_ATTR_UNUSED) {
+ assert(def->priv_spec <= PRIV_VERSION_LATEST);
+ mcc->def->priv_spec = def->priv_spec;
+ }
+ if (def->vext_spec != RISCV_PROFILE_ATTR_UNUSED) {
+ assert(def->vext_spec != 0);
+ mcc->def->vext_spec = def->vext_spec;
+ }
+ mcc->def->misa_ext |= def->misa_ext;
+
+ riscv_cpu_cfg_merge(&mcc->def->cfg, &def->cfg);
}
if (!object_class_is_abstract(c)) {
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index f3ec4f33931..8259cb4deee 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -1992,10 +1992,12 @@ static const TypeInfo riscv_kvm_cpu_type_infos[] = {
#if defined(TARGET_RISCV32)
.class_data = &((const RISCVCPUDef) {
.misa_mxl_max = MXL_RV32,
+ .cfg.max_satp_mode = -1,
},
#elif defined(TARGET_RISCV64)
.class_data = &((const RISCVCPUDef) {
.misa_mxl_max = MXL_RV64,
+ .cfg.max_satp_mode = -1,
},
#endif
}
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 08/22] target/riscv: convert abstract CPU classes to RISCVCPUDef
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (6 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 07/22] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-02-28 10:27 ` [PATCH 09/22] target/riscv: do not make RISCVCPUConfig fields conditional Paolo Bonzini
` (14 subsequent siblings)
22 siblings, 0 replies; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
Start from the top of the hierarchy: dynamic and vendor CPUs are just
markers, whereas bare CPUs can have their instance_init function
replaced by RISCVCPUDef.
The only difference is that the maximum supported SATP mode has to
be specified separately for 32-bit and 64-bit modes.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 92 ++++++++++++++++++++++------------------------
2 files changed, 45 insertions(+), 48 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8c9e73c68cc..2a8e1aa7d12 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -537,6 +537,7 @@ typedef struct RISCVCPUDef {
int priv_spec;
int32_t vext_spec;
RISCVCPUConfig cfg;
+ bool bare;
} RISCVCPUDef;
/**
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c513d7ce32d..e9d8126360e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1472,8 +1472,8 @@ static void riscv_cpu_init(Object *obj)
* for all CPUs. Each accelerator will decide what to do when
* users disable them.
*/
- RISCV_CPU(obj)->cfg.ext_zicntr = true;
- RISCV_CPU(obj)->cfg.ext_zihpm = true;
+ RISCV_CPU(obj)->cfg.ext_zicntr = !mcc->def->bare;
+ RISCV_CPU(obj)->cfg.ext_zihpm = !mcc->def->bare;
/* Default values for non-bool cpu properties */
cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, 16);
@@ -1499,36 +1499,6 @@ static void riscv_cpu_init(Object *obj)
}
}
-static void riscv_bare_cpu_init(Object *obj)
-{
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- /*
- * Bare CPUs do not inherit the timer and performance
- * counters from the parent class (see riscv_cpu_init()
- * for info on why the parent enables them).
- *
- * Users have to explicitly enable these counters for
- * bare CPUs.
- */
- cpu->cfg.ext_zicntr = false;
- cpu->cfg.ext_zihpm = false;
-
- /* Set to QEMU's first supported priv version */
- cpu->env.priv_ver = PRIV_VERSION_1_10_0;
-
- /*
- * Support all available satp_mode settings. The default
- * value will be set to MBARE if the user doesn't set
- * satp_mode manually (see set_satp_mode_default()).
- */
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(RISCV_CPU(obj),
- riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
- VM_1_10_SV32 : VM_1_10_SV57);
-#endif
-}
-
typedef struct misa_ext_info {
const char *name;
const char *description;
@@ -2987,6 +2957,7 @@ static void riscv_cpu_class_base_init(ObjectClass *c, void *data)
if (data) {
const RISCVCPUDef *def = data;
+ mcc->def->bare |= def->bare;
if (def->misa_mxl_max) {
assert(def->misa_mxl_max <= MXL_RV128);
mcc->def->misa_mxl_max = def->misa_mxl_max;
@@ -3131,6 +3102,18 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
}), \
}
+#define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \
+ { \
+ .name = (type_name), \
+ .parent = (parent_type_name), \
+ .abstract = true, \
+ .class_data = (void*) &((const RISCVCPUDef) { \
+ .priv_spec = RISCV_PROFILE_ATTR_UNUSED, \
+ .vext_spec = RISCV_PROFILE_ATTR_UNUSED, \
+ __VA_ARGS__ \
+ }), \
+ }
+
#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max_, initfn) \
{ \
.name = (type_name), \
@@ -3154,22 +3137,35 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.class_init = riscv_cpu_common_class_init,
.class_base_init = riscv_cpu_class_base_init,
},
- {
- .name = TYPE_RISCV_DYNAMIC_CPU,
- .parent = TYPE_RISCV_CPU,
- .abstract = true,
- },
- {
- .name = TYPE_RISCV_VENDOR_CPU,
- .parent = TYPE_RISCV_CPU,
- .abstract = true,
- },
- {
- .name = TYPE_RISCV_BARE_CPU,
- .parent = TYPE_RISCV_CPU,
- .instance_init = riscv_bare_cpu_init,
- .abstract = true,
- },
+
+ DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_DYNAMIC_CPU, TYPE_RISCV_CPU),
+ DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_VENDOR_CPU, TYPE_RISCV_CPU),
+ DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_BARE_CPU, TYPE_RISCV_CPU,
+ /*
+ * Bare CPUs do not inherit the timer and performance
+ * counters from the parent class (see riscv_cpu_init()
+ * for info on why the parent enables them).
+ *
+ * Users have to explicitly enable these counters for
+ * bare CPUs.
+ */
+ .bare = true,
+
+ /* Set to QEMU's first supported priv version */
+ .priv_spec = PRIV_VERSION_1_10_0,
+
+ /*
+ * Support all available satp_mode settings. By default
+ * only MBARE will be available if the user doesn't enable
+ * a mode manually (see riscv_cpu_satp_mode_finalize()).
+ */
+#ifdef TARGET_RISCV32
+ .cfg.max_satp_mode = VM_1_10_SV32,
+#else
+ .cfg.max_satp_mode = VM_1_10_SV57,
+#endif
+ ),
+
#if defined(TARGET_RISCV32)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_init),
#elif defined(TARGET_RISCV64)
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 09/22] target/riscv: do not make RISCVCPUConfig fields conditional
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (7 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 08/22] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-02-28 10:27 ` [PATCH 10/22] target/riscv: convert profile CPU models to RISCVCPUDef Paolo Bonzini
` (13 subsequent siblings)
22 siblings, 0 replies; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
Avoid the need for #ifdefs in CPU declarations, keeping them
simple. After all class_data used to be specified for all
emulators, not just system ones.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu_cfg_fields.h.inc | 2 --
target/riscv/cpu.c | 3 ---
2 files changed, 5 deletions(-)
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index a42f298017f..a08d85aec26 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -159,9 +159,7 @@ TYPED_FIELD(uint16_t, cbom_blocksize)
TYPED_FIELD(uint16_t, cbop_blocksize)
TYPED_FIELD(uint16_t, cboz_blocksize)
-#ifndef CONFIG_USER_ONLY
TYPED_FIELD(int8_t, max_satp_mode)
-#endif
#undef BOOL_FIELD
#undef TYPED_FIELD
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e9d8126360e..cbb6cde082b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1483,10 +1483,7 @@ static void riscv_cpu_init(Object *obj)
cpu->cfg.cbop_blocksize = 64;
cpu->cfg.cboz_blocksize = 64;
cpu->env.vext_ver = VEXT_VERSION_1_00_0;
-
-#ifndef CONFIG_USER_ONLY
cpu->cfg.max_satp_mode = -1;
-#endif /* CONFIG_USER_ONLY */
env->misa_ext_mask = env->misa_ext = mcc->def->misa_ext;
riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg);
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 10/22] target/riscv: convert profile CPU models to RISCVCPUDef
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (8 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 09/22] target/riscv: do not make RISCVCPUConfig fields conditional Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-02-28 10:27 ` [PATCH 11/22] target/riscv: convert bare " Paolo Bonzini
` (12 subsequent siblings)
22 siblings, 0 replies; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
Profile CPUs reuse the instance_init function for bare CPUs; make them
proper subclasses instead. Enabling a profile is now done based on the
RISCVCPUDef struct: even though there is room for only one in RISCVCPUDef,
subclasses check that the parent class's profile is enabled through the
parent profile mechanism.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 59 +++++++++++++++++++++++++++++-----------------
2 files changed, 38 insertions(+), 22 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2a8e1aa7d12..f00089bd733 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -533,6 +533,7 @@ struct ArchCPU {
typedef struct RISCVCPUDef {
RISCVMXL misa_mxl_max; /* max mxl for this cpu */
+ RISCVCPUProfile *profile;
uint32_t misa_ext;
int priv_spec;
int32_t vext_spec;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cbb6cde082b..732a0540660 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1485,6 +1485,10 @@ static void riscv_cpu_init(Object *obj)
cpu->env.vext_ver = VEXT_VERSION_1_00_0;
cpu->cfg.max_satp_mode = -1;
+ if (mcc->def->profile) {
+ mcc->def->profile->enabled = true;
+ }
+
env->misa_ext_mask = env->misa_ext = mcc->def->misa_ext;
riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg);
@@ -2859,22 +2863,6 @@ static const Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
};
-#if defined(TARGET_RISCV64)
-static void rva22u64_profile_cpu_init(Object *obj)
-{
- rv64i_bare_cpu_init(obj);
-
- RVA22U64.enabled = true;
-}
-
-static void rva22s64_profile_cpu_init(Object *obj)
-{
- rv64i_bare_cpu_init(obj);
-
- RVA22S64.enabled = true;
-}
-#endif
-
static const gchar *riscv_gdb_arch_name(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
@@ -2941,6 +2929,22 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data)
device_class_set_props(dc, riscv_cpu_properties);
}
+static bool profile_has_parent(RISCVCPUProfile *trial, RISCVCPUProfile *parent)
+{
+ if (!parent) {
+ return true;
+ }
+
+ while (parent != trial) {
+ trial = trial->parent;
+ if (!trial) {
+ return false;
+ }
+ }
+
+ return true;
+}
+
static void riscv_cpu_class_base_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
@@ -2955,6 +2959,11 @@ static void riscv_cpu_class_base_init(ObjectClass *c, void *data)
if (data) {
const RISCVCPUDef *def = data;
mcc->def->bare |= def->bare;
+ if (def->profile) {
+ assert(profile_has_parent(def->profile, mcc->def->profile));
+ assert(mcc->def->bare);
+ mcc->def->profile = def->profile;
+ }
if (def->misa_mxl_max) {
assert(def->misa_mxl_max <= MXL_RV128);
mcc->def->misa_mxl_max = def->misa_mxl_max;
@@ -3111,16 +3120,21 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
}), \
}
-#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max_, initfn) \
+#define DEFINE_RISCV_CPU(type_name, parent_type_name, ...) \
{ \
.name = (type_name), \
- .parent = TYPE_RISCV_BARE_CPU, \
- .instance_init = (initfn), \
+ .parent = (parent_type_name), \
.class_data = (void*) &((const RISCVCPUDef) { \
- .misa_mxl_max = (misa_mxl_max_), \
+ .priv_spec = RISCV_PROFILE_ATTR_UNUSED, \
+ .vext_spec = RISCV_PROFILE_ATTR_UNUSED, \
+ __VA_ARGS__ \
}), \
}
+#define DEFINE_PROFILE_CPU(type_name, parent_type_name, profile_) \
+ DEFINE_RISCV_CPU(type_name, parent_type_name, \
+ .profile = &(profile_))
+
static const TypeInfo riscv_cpu_type_infos[] = {
{
.name = TYPE_RISCV_CPU,
@@ -3199,8 +3213,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#endif /* CONFIG_TCG */
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu_init),
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu_init),
- DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init),
- DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init),
+
+ DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, TYPE_RISCV_CPU_RV64I, RVA22U64),
+ DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, TYPE_RISCV_CPU_RV64I, RVA22S64),
#endif /* TARGET_RISCV64 */
};
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 11/22] target/riscv: convert bare CPU models to RISCVCPUDef
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (9 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 10/22] target/riscv: convert profile CPU models to RISCVCPUDef Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-02-28 10:27 ` [PATCH 12/22] target/riscv: convert dynamic " Paolo Bonzini
` (11 subsequent siblings)
22 siblings, 0 replies; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 55 ++++++++++++++--------------------------------
1 file changed, 17 insertions(+), 38 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 732a0540660..feff1c91a00 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -732,18 +732,6 @@ static void rv128_base_cpu_init(Object *obj)
}
#endif /* CONFIG_TCG */
-static void rv64i_bare_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- riscv_cpu_set_misa_ext(env, RVI);
-}
-
-static void rv64e_bare_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- riscv_cpu_set_misa_ext(env, RVE);
-}
-
#endif /* !TARGET_RISCV64 */
#if defined(TARGET_RISCV32) || \
@@ -836,18 +824,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
cpu->cfg.ext_zicsr = true;
cpu->cfg.pmp = true;
}
-
-static void rv32i_bare_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- riscv_cpu_set_misa_ext(env, RVI);
-}
-
-static void rv32e_bare_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- riscv_cpu_set_misa_ext(env, RVE);
-}
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -3098,16 +3074,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
}), \
}
-#define DEFINE_BARE_CPU(type_name, misa_mxl_max_, initfn) \
- { \
- .name = (type_name), \
- .parent = TYPE_RISCV_BARE_CPU, \
- .instance_init = (initfn), \
- .class_data = (void*) &((const RISCVCPUDef) { \
- .misa_mxl_max = (misa_mxl_max_), \
- }), \
- }
-
#define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \
{ \
.name = (type_name), \
@@ -3190,8 +3156,15 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_nommu_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_cpu_init),
- DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, MXL_RV32, rv32i_bare_cpu_init),
- DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_cpu_init),
+
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU,
+ .misa_mxl_max = MXL_RV32,
+ .misa_ext = RVI
+ ),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32E, TYPE_RISCV_BARE_CPU,
+ .misa_mxl_max = MXL_RV32,
+ .misa_ext = RVE
+ ),
#endif
#if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
@@ -3211,8 +3184,14 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#ifdef CONFIG_TCG
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init),
#endif /* CONFIG_TCG */
- DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu_init),
- DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64I, TYPE_RISCV_BARE_CPU,
+ .misa_mxl_max = MXL_RV64,
+ .misa_ext = RVI
+ ),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64E, TYPE_RISCV_BARE_CPU,
+ .misa_mxl_max = MXL_RV64,
+ .misa_ext = RVE
+ ),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, TYPE_RISCV_CPU_RV64I, RVA22U64),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, TYPE_RISCV_CPU_RV64I, RVA22S64),
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 12/22] target/riscv: convert dynamic CPU models to RISCVCPUDef
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (10 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 11/22] target/riscv: convert bare " Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-02-28 10:27 ` [PATCH 13/22] target/riscv: convert SiFive E " Paolo Bonzini
` (10 subsequent siblings)
22 siblings, 0 replies; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 110 +++++++++++++--------------------------------
1 file changed, 30 insertions(+), 80 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index feff1c91a00..c605efa2b92 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -483,38 +483,7 @@ static void set_satp_mode_default_map(RISCVCPU *cpu)
}
#endif
-static void riscv_max_cpu_init(Object *obj)
-{
- RISCVCPU *cpu = RISCV_CPU(obj);
- CPURISCVState *env = &cpu->env;
-
- cpu->cfg.mmu = true;
- cpu->cfg.pmp = true;
-
- env->priv_ver = PRIV_VERSION_LATEST;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(RISCV_CPU(obj),
- riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
- VM_1_10_SV32 : VM_1_10_SV57);
-#endif
-}
-
#if defined(TARGET_RISCV64)
-static void rv64_base_cpu_init(Object *obj)
-{
- RISCVCPU *cpu = RISCV_CPU(obj);
- CPURISCVState *env = &cpu->env;
-
- cpu->cfg.mmu = true;
- cpu->cfg.pmp = true;
-
- /* Set latest version of privileged specification */
- env->priv_ver = PRIV_VERSION_LATEST;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
-#endif
-}
-
static void rv64_sifive_u_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
@@ -715,43 +684,11 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
#endif
}
-#ifdef CONFIG_TCG
-static void rv128_base_cpu_init(Object *obj)
-{
- RISCVCPU *cpu = RISCV_CPU(obj);
- CPURISCVState *env = &cpu->env;
-
- cpu->cfg.mmu = true;
- cpu->cfg.pmp = true;
-
- /* Set latest version of privileged specification */
- env->priv_ver = PRIV_VERSION_LATEST;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
-#endif
-}
-#endif /* CONFIG_TCG */
-
#endif /* !TARGET_RISCV64 */
#if defined(TARGET_RISCV32) || \
(defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
-static void rv32_base_cpu_init(Object *obj)
-{
- RISCVCPU *cpu = RISCV_CPU(obj);
- CPURISCVState *env = &cpu->env;
-
- cpu->cfg.mmu = true;
- cpu->cfg.pmp = true;
-
- /* Set latest version of privileged specification */
- env->priv_ver = PRIV_VERSION_LATEST;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
-#endif
-}
-
static void rv32_sifive_u_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
@@ -3054,16 +2991,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
}
#endif
-#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max_, initfn) \
- { \
- .name = (type_name), \
- .parent = TYPE_RISCV_DYNAMIC_CPU, \
- .instance_init = (initfn), \
- .class_data = (void*) &((const RISCVCPUDef) { \
- .misa_mxl_max = (misa_mxl_max_), \
- }), \
- }
-
#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max_, initfn) \
{ \
.name = (type_name), \
@@ -3115,7 +3042,12 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.class_base_init = riscv_cpu_class_base_init,
},
- DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_DYNAMIC_CPU, TYPE_RISCV_CPU),
+ DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_DYNAMIC_CPU, TYPE_RISCV_CPU,
+ .cfg.mmu = true,
+ .cfg.pmp = true,
+ .priv_spec = PRIV_VERSION_LATEST,
+ ),
+
DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_VENDOR_CPU, TYPE_RISCV_CPU),
DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_BARE_CPU, TYPE_RISCV_CPU,
/*
@@ -3143,15 +3075,23 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#endif
),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX, TYPE_RISCV_DYNAMIC_CPU,
#if defined(TARGET_RISCV32)
- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_init),
+ .misa_mxl_max = MXL_RV32,
+ .cfg.max_satp_mode = VM_1_10_SV32,
#elif defined(TARGET_RISCV64)
- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_init),
+ .misa_mxl_max = MXL_RV64,
+ .cfg.max_satp_mode = VM_1_10_SV57,
#endif
+ ),
#if defined(TARGET_RISCV32) || \
(defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32, rv32_base_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU,
+ .cfg.max_satp_mode = VM_1_10_SV32,
+ .misa_mxl_max = MXL_RV32,
+ ),
+
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_nommu_cpu_init),
@@ -3168,11 +3108,18 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#endif
#if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX32, MXL_RV32, riscv_max_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX32, TYPE_RISCV_DYNAMIC_CPU,
+ .cfg.max_satp_mode = VM_1_10_SV32,
+ .misa_mxl_max = MXL_RV32,
+ ),
#endif
#if defined(TARGET_RISCV64)
- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE64, TYPE_RISCV_DYNAMIC_CPU,
+ .cfg.max_satp_mode = VM_1_10_SV57,
+ .misa_mxl_max = MXL_RV64,
+ ),
+
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cpu_init),
@@ -3182,7 +3129,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
MXL_RV64, rv64_xiangshan_nanhu_cpu_init),
#ifdef CONFIG_TCG
- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
+ .cfg.max_satp_mode = VM_1_10_SV57,
+ .misa_mxl_max = MXL_RV128,
+ ),
#endif /* CONFIG_TCG */
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64I, TYPE_RISCV_BARE_CPU,
.misa_mxl_max = MXL_RV64,
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 13/22] target/riscv: convert SiFive E CPU models to RISCVCPUDef
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (11 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 12/22] target/riscv: convert dynamic " Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-02-28 10:27 ` [PATCH 14/22] target/riscv: convert ibex " Paolo Bonzini
` (9 subsequent siblings)
22 siblings, 0 replies; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 74 ++++++++++++------------------------------
2 files changed, 21 insertions(+), 54 deletions(-)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index d56b067bf24..bfe1455254c 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -42,6 +42,7 @@
#define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
+#define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c605efa2b92..049d3f90f47 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -501,23 +501,6 @@ static void rv64_sifive_u_cpu_init(Object *obj)
cpu->cfg.pmp = true;
}
-static void rv64_sifive_e_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);
- env->priv_ver = PRIV_VERSION_1_10_0;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
-#endif
-
- /* inherited from parent obj via riscv_cpu_init() */
- cpu->cfg.ext_zifencei = true;
- cpu->cfg.ext_zicsr = true;
- cpu->cfg.pmp = true;
-}
-
static void rv64_thead_c906_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -706,23 +689,6 @@ static void rv32_sifive_u_cpu_init(Object *obj)
cpu->cfg.pmp = true;
}
-static void rv32_sifive_e_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);
- env->priv_ver = PRIV_VERSION_1_10_0;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
-#endif
-
- /* inherited from parent obj via riscv_cpu_init() */
- cpu->cfg.ext_zifencei = true;
- cpu->cfg.ext_zicsr = true;
- cpu->cfg.pmp = true;
-}
-
static void rv32_ibex_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -744,23 +710,6 @@ static void rv32_ibex_cpu_init(Object *obj)
cpu->cfg.ext_zbc = true;
cpu->cfg.ext_zbs = true;
}
-
-static void rv32_imafcu_nommu_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU);
- env->priv_ver = PRIV_VERSION_1_10_0;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
-#endif
-
- /* inherited from parent obj via riscv_cpu_init() */
- cpu->cfg.ext_zifencei = true;
- cpu->cfg.ext_zicsr = true;
- cpu->cfg.pmp = true;
-}
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -3085,6 +3034,15 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#endif
),
+ DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E, TYPE_RISCV_VENDOR_CPU,
+ .misa_ext = RVI | RVM | RVA | RVC | RVU,
+ .priv_spec = PRIV_VERSION_1_10_0,
+ .cfg.max_satp_mode = VM_1_10_MBARE,
+ .cfg.ext_zifencei = true,
+ .cfg.ext_zicsr = true,
+ .cfg.pmp = true
+ ),
+
#if defined(TARGET_RISCV32) || \
(defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU,
@@ -3093,8 +3051,14 @@ static const TypeInfo riscv_cpu_type_infos[] = {
),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_init),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_cpu_init),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_nommu_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E,
+ .misa_mxl_max = MXL_RV32
+ ),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E34, TYPE_RISCV_CPU_SIFIVE_E,
+ .misa_mxl_max = MXL_RV32,
+ .misa_ext = RVF, /* IMAFCU */
+ ),
+
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_cpu_init),
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU,
@@ -3120,7 +3084,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.misa_mxl_max = MXL_RV64,
),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E,
+ .misa_mxl_max = MXL_RV64
+ ),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_cpu_init),
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 14/22] target/riscv: convert ibex CPU models to RISCVCPUDef
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (12 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 13/22] target/riscv: convert SiFive E " Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-02-28 10:27 ` [PATCH 15/22] target/riscv: convert SiFive U " Paolo Bonzini
` (8 subsequent siblings)
22 siblings, 0 replies; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 39 ++++++++++++++++-----------------------
1 file changed, 16 insertions(+), 23 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 049d3f90f47..fc5bf6def8c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -688,28 +688,6 @@ static void rv32_sifive_u_cpu_init(Object *obj)
cpu->cfg.mmu = true;
cpu->cfg.pmp = true;
}
-
-static void rv32_ibex_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVI | RVM | RVC | RVU);
- env->priv_ver = PRIV_VERSION_1_12_0;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
-#endif
- /* inherited from parent obj via riscv_cpu_init() */
- cpu->cfg.ext_zifencei = true;
- cpu->cfg.ext_zicsr = true;
- cpu->cfg.pmp = true;
- cpu->cfg.ext_smepmp = true;
-
- cpu->cfg.ext_zba = true;
- cpu->cfg.ext_zbb = true;
- cpu->cfg.ext_zbc = true;
- cpu->cfg.ext_zbs = true;
-}
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -3050,7 +3028,22 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.misa_mxl_max = MXL_RV32,
),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_IBEX, TYPE_RISCV_VENDOR_CPU,
+ .misa_mxl_max = MXL_RV32,
+ .misa_ext = RVI | RVM | RVC | RVU,
+ .priv_spec = PRIV_VERSION_1_12_0,
+ .cfg.max_satp_mode = VM_1_10_MBARE,
+ .cfg.ext_zifencei = true,
+ .cfg.ext_zicsr = true,
+ .cfg.pmp = true,
+ .cfg.ext_smepmp = true,
+
+ .cfg.ext_zba = true,
+ .cfg.ext_zbb = true,
+ .cfg.ext_zbc = true,
+ .cfg.ext_zbs = true
+ ),
+
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E,
.misa_mxl_max = MXL_RV32
),
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 15/22] target/riscv: convert SiFive U models to RISCVCPUDef
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (13 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 14/22] target/riscv: convert ibex " Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-02-28 10:27 ` [PATCH 16/22] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
` (7 subsequent siblings)
22 siblings, 0 replies; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 75 +++++++++++++++++++-----------------------
2 files changed, 35 insertions(+), 41 deletions(-)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index bfe1455254c..398cb4f583c 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -46,6 +46,7 @@
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
+#define TYPE_RISCV_CPU_SIFIVE_U RISCV_CPU_TYPE_NAME("sifive-u")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fc5bf6def8c..e05fb5d07e0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -484,23 +484,6 @@ static void set_satp_mode_default_map(RISCVCPU *cpu)
#endif
#if defined(TARGET_RISCV64)
-static void rv64_sifive_u_cpu_init(Object *obj)
-{
- RISCVCPU *cpu = RISCV_CPU(obj);
- CPURISCVState *env = &cpu->env;
- riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
- env->priv_ver = PRIV_VERSION_1_10_0;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
-#endif
-
- /* inherited from parent obj via riscv_cpu_init() */
- cpu->cfg.ext_zifencei = true;
- cpu->cfg.ext_zicsr = true;
- cpu->cfg.mmu = true;
- cpu->cfg.pmp = true;
-}
-
static void rv64_thead_c906_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -669,27 +652,6 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
#endif /* !TARGET_RISCV64 */
-#if defined(TARGET_RISCV32) || \
- (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
-
-static void rv32_sifive_u_cpu_init(Object *obj)
-{
- RISCVCPU *cpu = RISCV_CPU(obj);
- CPURISCVState *env = &cpu->env;
- riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
- env->priv_ver = PRIV_VERSION_1_10_0;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
-#endif
-
- /* inherited from parent obj via riscv_cpu_init() */
- cpu->cfg.ext_zifencei = true;
- cpu->cfg.ext_zicsr = true;
- cpu->cfg.mmu = true;
- cpu->cfg.pmp = true;
-}
-#endif
-
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
@@ -2807,6 +2769,17 @@ static void riscv_cpu_class_base_init(ObjectClass *c, void *data)
if (def->misa_mxl_max) {
assert(def->misa_mxl_max <= MXL_RV128);
mcc->def->misa_mxl_max = def->misa_mxl_max;
+
+#ifndef CONFIG_USER_ONLY
+ /*
+ * Hack to simplify CPU class hierarchies that include both 32- and
+ * 64-bit models: reduce SV39/48/57/64 to SV32 for 32-bit models.
+ */
+ if (mcc->def->misa_mxl_max == MXL_RV32 &&
+ !valid_vm_1_10_32[mcc->def->cfg.max_satp_mode]) {
+ mcc->def->cfg.max_satp_mode = VM_1_10_SV32;
+ }
+#endif
}
if (def->priv_spec != RISCV_PROFILE_ATTR_UNUSED) {
assert(def->priv_spec <= PRIV_VERSION_LATEST);
@@ -3021,6 +2994,17 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.pmp = true
),
+ DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U, TYPE_RISCV_VENDOR_CPU,
+ .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU,
+ .priv_spec = PRIV_VERSION_1_10_0,
+
+ .cfg.max_satp_mode = VM_1_10_SV39,
+ .cfg.ext_zifencei = true,
+ .cfg.ext_zicsr = true,
+ .cfg.mmu = true,
+ .cfg.pmp = true
+ ),
+
#if defined(TARGET_RISCV32) || \
(defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU,
@@ -3052,7 +3036,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.misa_ext = RVF, /* IMAFCU */
),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U34, TYPE_RISCV_CPU_SIFIVE_U,
+ .misa_mxl_max = MXL_RV32,
+ ),
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU,
.misa_mxl_max = MXL_RV32,
@@ -3080,8 +3066,15 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E,
.misa_mxl_max = MXL_RV64
),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cpu_init),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cpu_init),
+
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U54, TYPE_RISCV_CPU_SIFIVE_U,
+ .misa_mxl_max = MXL_RV64,
+ ),
+
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SHAKTI_C, TYPE_RISCV_CPU_SIFIVE_U,
+ .misa_mxl_max = MXL_RV64,
+ ),
+
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalon_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init),
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 16/22] target/riscv: th: make CSR insertion test a bit more intuitive
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (14 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 15/22] target/riscv: convert SiFive U " Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-02-28 10:27 ` [PATCH 17/22] target/riscv: generalize custom CSR functionality Paolo Bonzini
` (6 subsequent siblings)
22 siblings, 0 replies; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
In preparation for generalizing the custom CSR functionality,
make the test return bool instead of int. Make the insertion_test
optional, too.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/th_csr.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
index 6c970d4e813..969a9fe3c80 100644
--- a/target/riscv/th_csr.c
+++ b/target/riscv/th_csr.c
@@ -29,7 +29,7 @@
typedef struct {
int csrno;
- int (*insertion_test)(RISCVCPU *cpu);
+ bool (*insertion_test)(RISCVCPU *cpu);
riscv_csr_operations csr_ops;
} riscv_csr;
@@ -42,13 +42,9 @@ static RISCVException smode(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
-static int test_thead_mvendorid(RISCVCPU *cpu)
+static bool test_thead_mvendorid(RISCVCPU *cpu)
{
- if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
- return -1;
- }
-
- return 0;
+ return cpu->cfg.mvendorid == THEAD_VENDOR_ID;
}
static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
@@ -66,13 +62,12 @@ static riscv_csr th_csr_list[] = {
.csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
}
};
-
void th_register_custom_csrs(RISCVCPU *cpu)
{
for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
int csrno = th_csr_list[i].csrno;
riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
- if (!th_csr_list[i].insertion_test(cpu)) {
+ if (!th_csr_list[i].insertion_test || th_csr_list[i].insertion_test(cpu)) {
riscv_set_csr_ops(csrno, csr_ops);
}
}
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 17/22] target/riscv: generalize custom CSR functionality
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (15 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 16/22] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-02-28 10:27 ` [PATCH 18/22] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
` (5 subsequent siblings)
22 siblings, 0 replies; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
While at it, constify it so that the RISCVCSR array in RISCVCPUDef
can also be const.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.h | 15 ++++++++++++---
target/riscv/cpu.c | 25 ++++++++++++++++++++++++-
target/riscv/csr.c | 2 +-
target/riscv/th_csr.c | 21 +++------------------
4 files changed, 40 insertions(+), 23 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f00089bd733..a8268599f23 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -531,6 +531,8 @@ struct ArchCPU {
const GPtrArray *decoders;
};
+typedef struct RISCVCSR RISCVCSR;
+
typedef struct RISCVCPUDef {
RISCVMXL misa_mxl_max; /* max mxl for this cpu */
RISCVCPUProfile *profile;
@@ -539,6 +541,7 @@ typedef struct RISCVCPUDef {
int32_t vext_spec;
RISCVCPUConfig cfg;
bool bare;
+ const RISCVCSR *custom_csrs;
} RISCVCPUDef;
/**
@@ -874,6 +877,12 @@ typedef struct {
uint32_t min_priv_ver;
} riscv_csr_operations;
+struct RISCVCSR {
+ int csrno;
+ bool (*insertion_test)(RISCVCPU *cpu);
+ riscv_csr_operations csr_ops;
+};
+
/* CSR function table constants */
enum {
CSR_TABLE_SIZE = 0x1000
@@ -928,7 +937,7 @@ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[];
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
-void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
+void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops);
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
@@ -937,8 +946,8 @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
-/* Implemented in th_csr.c */
-void th_register_custom_csrs(RISCVCPU *cpu);
+/* In th_csr.c */
+extern const RISCVCSR th_csr_list[];
const char *priv_spec_to_str(int priv_version);
#endif /* RISCV_CPU_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e05fb5d07e0..4d6756a97ce 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -483,6 +483,19 @@ static void set_satp_mode_default_map(RISCVCPU *cpu)
}
#endif
+#ifndef CONFIG_USER_ONLY
+static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list)
+{
+ for (size_t i = 0; csr_list[i].csr_ops.name; i++) {
+ int csrno = csr_list[i].csrno;
+ const riscv_csr_operations *csr_ops = &csr_list[i].csr_ops;
+ if (!csr_list[i].insertion_test || csr_list[i].insertion_test(cpu)) {
+ riscv_set_csr_ops(csrno, csr_ops);
+ }
+ }
+}
+#endif
+
#if defined(TARGET_RISCV64)
static void rv64_thead_c906_cpu_init(Object *obj)
{
@@ -509,7 +522,7 @@ static void rv64_thead_c906_cpu_init(Object *obj)
cpu->cfg.mvendorid = THEAD_VENDOR_ID;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_SV39);
- th_register_custom_csrs(cpu);
+ riscv_register_custom_csrs(cpu, th_csr_list);
#endif
/* inherited from parent obj via riscv_cpu_init() */
@@ -1300,6 +1313,11 @@ static void riscv_cpu_init(Object *obj)
if (mcc->def->vext_spec != RISCV_PROFILE_ATTR_UNUSED) {
cpu->env.vext_ver = mcc->def->vext_spec;
}
+#ifndef CONFIG_USER_ONLY
+ if (mcc->def->custom_csrs) {
+ riscv_register_custom_csrs(cpu, mcc->def->custom_csrs);
+ }
+#endif
}
typedef struct misa_ext_info {
@@ -2792,6 +2810,11 @@ static void riscv_cpu_class_base_init(ObjectClass *c, void *data)
mcc->def->misa_ext |= def->misa_ext;
riscv_cpu_cfg_merge(&mcc->def->cfg, &def->cfg);
+
+ if (def->custom_csrs) {
+ assert(!mcc->def->custom_csrs);
+ mcc->def->custom_csrs = def->custom_csrs;
+ }
}
if (!object_class_is_abstract(c)) {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 78db9aeda57..7842c525149 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -37,7 +37,7 @@ void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
*ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
}
-void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
+void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops)
{
csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
}
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
index 969a9fe3c80..49eb7bbab5f 100644
--- a/target/riscv/th_csr.c
+++ b/target/riscv/th_csr.c
@@ -27,12 +27,6 @@
#define TH_SXSTATUS_MAEE BIT(21)
#define TH_SXSTATUS_THEADISAEE BIT(22)
-typedef struct {
- int csrno;
- bool (*insertion_test)(RISCVCPU *cpu);
- riscv_csr_operations csr_ops;
-} riscv_csr;
-
static RISCVException smode(CPURISCVState *env, int csrno)
{
if (riscv_has_ext(env, RVS)) {
@@ -55,20 +49,11 @@ static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
-static riscv_csr th_csr_list[] = {
+const RISCVCSR th_csr_list[] = {
{
.csrno = CSR_TH_SXSTATUS,
.insertion_test = test_thead_mvendorid,
.csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
- }
+ },
+ { }
};
-void th_register_custom_csrs(RISCVCPU *cpu)
-{
- for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
- int csrno = th_csr_list[i].csrno;
- riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
- if (!th_csr_list[i].insertion_test || th_csr_list[i].insertion_test(cpu)) {
- riscv_set_csr_ops(csrno, csr_ops);
- }
- }
-}
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 18/22] target/riscv: convert TT C906 to RISCVCPUDef
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (16 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 17/22] target/riscv: generalize custom CSR functionality Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-02-28 10:27 ` [PATCH 19/22] target/riscv: convert TT Ascalon " Paolo Bonzini
` (4 subsequent siblings)
22 siblings, 0 replies; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 61 +++++++++++++++++++++-------------------------
1 file changed, 28 insertions(+), 33 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4d6756a97ce..a249e48da6c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -497,38 +497,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list)
#endif
#if defined(TARGET_RISCV64)
-static void rv64_thead_c906_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU);
- env->priv_ver = PRIV_VERSION_1_11_0;
-
- cpu->cfg.ext_zfa = true;
- cpu->cfg.ext_zfh = true;
- cpu->cfg.mmu = true;
- cpu->cfg.ext_xtheadba = true;
- cpu->cfg.ext_xtheadbb = true;
- cpu->cfg.ext_xtheadbs = true;
- cpu->cfg.ext_xtheadcmo = true;
- cpu->cfg.ext_xtheadcondmov = true;
- cpu->cfg.ext_xtheadfmemidx = true;
- cpu->cfg.ext_xtheadmac = true;
- cpu->cfg.ext_xtheadmemidx = true;
- cpu->cfg.ext_xtheadmempair = true;
- cpu->cfg.ext_xtheadsync = true;
-
- cpu->cfg.mvendorid = THEAD_VENDOR_ID;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_SV39);
- riscv_register_custom_csrs(cpu, th_csr_list);
-#endif
-
- /* inherited from parent obj via riscv_cpu_init() */
- cpu->cfg.pmp = true;
-}
-
static void rv64_veyron_v1_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -3098,7 +3066,34 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.misa_mxl_max = MXL_RV64,
),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C906, TYPE_RISCV_VENDOR_CPU,
+ .misa_mxl_max = MXL_RV64,
+ .misa_ext = RVG | RVC | RVS | RVU,
+ .priv_spec = PRIV_VERSION_1_11_0,
+
+ .cfg.ext_zfa = true,
+ .cfg.ext_zfh = true,
+ .cfg.mmu = true,
+ .cfg.ext_xtheadba = true,
+ .cfg.ext_xtheadbb = true,
+ .cfg.ext_xtheadbs = true,
+ .cfg.ext_xtheadcmo = true,
+ .cfg.ext_xtheadcondmov = true,
+ .cfg.ext_xtheadfmemidx = true,
+ .cfg.ext_xtheadmac = true,
+ .cfg.ext_xtheadmemidx = true,
+ .cfg.ext_xtheadmempair = true,
+ .cfg.ext_xtheadsync = true,
+ .cfg.pmp = true,
+
+ .cfg.mvendorid = THEAD_VENDOR_ID,
+
+ .cfg.max_satp_mode = VM_1_10_SV39,
+#ifndef CONFIG_USER_ONLY
+ .custom_csrs = th_csr_list,
+#endif
+ ),
+
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalon_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 19/22] target/riscv: convert TT Ascalon to RISCVCPUDef
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (17 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 18/22] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-02-28 10:27 ` [PATCH 20/22] target/riscv: convert Ventana V1 " Paolo Bonzini
` (3 subsequent siblings)
22 siblings, 0 replies; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 127 +++++++++++++++++++++------------------------
1 file changed, 60 insertions(+), 67 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a249e48da6c..52e33905d21 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -537,72 +537,6 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
#endif
}
-/* Tenstorrent Ascalon */
-static void rv64_tt_ascalon_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH | RVV);
- env->priv_ver = PRIV_VERSION_1_13_0;
-
- /* Enable ISA extensions */
- cpu->cfg.mmu = true;
- cpu->cfg.vlenb = 256 >> 3;
- cpu->cfg.elen = 64;
- cpu->env.vext_ver = VEXT_VERSION_1_00_0;
- cpu->cfg.rvv_ma_all_1s = true;
- cpu->cfg.rvv_ta_all_1s = true;
- cpu->cfg.misa_w = true;
- cpu->cfg.pmp = true;
- cpu->cfg.cbom_blocksize = 64;
- cpu->cfg.cbop_blocksize = 64;
- cpu->cfg.cboz_blocksize = 64;
- cpu->cfg.ext_zic64b = true;
- cpu->cfg.ext_zicbom = true;
- cpu->cfg.ext_zicbop = true;
- cpu->cfg.ext_zicboz = true;
- cpu->cfg.ext_zicntr = true;
- cpu->cfg.ext_zicond = true;
- cpu->cfg.ext_zicsr = true;
- cpu->cfg.ext_zifencei = true;
- cpu->cfg.ext_zihintntl = true;
- cpu->cfg.ext_zihintpause = true;
- cpu->cfg.ext_zihpm = true;
- cpu->cfg.ext_zimop = true;
- cpu->cfg.ext_zawrs = true;
- cpu->cfg.ext_zfa = true;
- cpu->cfg.ext_zfbfmin = true;
- cpu->cfg.ext_zfh = true;
- cpu->cfg.ext_zfhmin = true;
- cpu->cfg.ext_zcb = true;
- cpu->cfg.ext_zcmop = true;
- cpu->cfg.ext_zba = true;
- cpu->cfg.ext_zbb = true;
- cpu->cfg.ext_zbs = true;
- cpu->cfg.ext_zkt = true;
- cpu->cfg.ext_zvbb = true;
- cpu->cfg.ext_zvbc = true;
- cpu->cfg.ext_zvfbfmin = true;
- cpu->cfg.ext_zvfbfwma = true;
- cpu->cfg.ext_zvfh = true;
- cpu->cfg.ext_zvfhmin = true;
- cpu->cfg.ext_zvkng = true;
- cpu->cfg.ext_smaia = true;
- cpu->cfg.ext_smstateen = true;
- cpu->cfg.ext_ssaia = true;
- cpu->cfg.ext_sscofpmf = true;
- cpu->cfg.ext_sstc = true;
- cpu->cfg.ext_svade = true;
- cpu->cfg.ext_svinval = true;
- cpu->cfg.ext_svnapot = true;
- cpu->cfg.ext_svpbmt = true;
-
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_SV57);
-#endif
-}
-
static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -3094,7 +3028,66 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#endif
),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalon_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_TT_ASCALON, TYPE_RISCV_VENDOR_CPU,
+ .misa_mxl_max = MXL_RV64,
+ .misa_ext = RVG | RVC | RVS | RVU | RVH | RVV,
+ .priv_spec = PRIV_VERSION_1_13_0,
+ .vext_spec = VEXT_VERSION_1_00_0,
+
+ /* ISA extensions */
+ .cfg.mmu = true,
+ .cfg.vlenb = 256 >> 3,
+ .cfg.elen = 64,
+ .cfg.rvv_ma_all_1s = true,
+ .cfg.rvv_ta_all_1s = true,
+ .cfg.misa_w = true,
+ .cfg.pmp = true,
+ .cfg.cbom_blocksize = 64,
+ .cfg.cbop_blocksize = 64,
+ .cfg.cboz_blocksize = 64,
+ .cfg.ext_zic64b = true,
+ .cfg.ext_zicbom = true,
+ .cfg.ext_zicbop = true,
+ .cfg.ext_zicboz = true,
+ .cfg.ext_zicntr = true,
+ .cfg.ext_zicond = true,
+ .cfg.ext_zicsr = true,
+ .cfg.ext_zifencei = true,
+ .cfg.ext_zihintntl = true,
+ .cfg.ext_zihintpause = true,
+ .cfg.ext_zihpm = true,
+ .cfg.ext_zimop = true,
+ .cfg.ext_zawrs = true,
+ .cfg.ext_zfa = true,
+ .cfg.ext_zfbfmin = true,
+ .cfg.ext_zfh = true,
+ .cfg.ext_zfhmin = true,
+ .cfg.ext_zcb = true,
+ .cfg.ext_zcmop = true,
+ .cfg.ext_zba = true,
+ .cfg.ext_zbb = true,
+ .cfg.ext_zbs = true,
+ .cfg.ext_zkt = true,
+ .cfg.ext_zvbb = true,
+ .cfg.ext_zvbc = true,
+ .cfg.ext_zvfbfmin = true,
+ .cfg.ext_zvfbfwma = true,
+ .cfg.ext_zvfh = true,
+ .cfg.ext_zvfhmin = true,
+ .cfg.ext_zvkng = true,
+ .cfg.ext_smaia = true,
+ .cfg.ext_smstateen = true,
+ .cfg.ext_ssaia = true,
+ .cfg.ext_sscofpmf = true,
+ .cfg.ext_sstc = true,
+ .cfg.ext_svade = true,
+ .cfg.ext_svinval = true,
+ .cfg.ext_svnapot = true,
+ .cfg.ext_svpbmt = true,
+
+ .cfg.max_satp_mode = VM_1_10_SV57,
+ ),
+
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
MXL_RV64, rv64_xiangshan_nanhu_cpu_init),
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 20/22] target/riscv: convert Ventana V1 to RISCVCPUDef
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (18 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 19/22] target/riscv: convert TT Ascalon " Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-02-28 10:27 ` [PATCH 21/22] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
` (2 subsequent siblings)
22 siblings, 0 replies; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 75 ++++++++++++++++++++++------------------------
1 file changed, 35 insertions(+), 40 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 52e33905d21..a6c97a43799 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -497,45 +497,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list)
#endif
#if defined(TARGET_RISCV64)
-static void rv64_veyron_v1_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH);
- env->priv_ver = PRIV_VERSION_1_12_0;
-
- /* Enable ISA extensions */
- cpu->cfg.mmu = true;
- cpu->cfg.ext_zifencei = true;
- cpu->cfg.ext_zicsr = true;
- cpu->cfg.pmp = true;
- cpu->cfg.ext_zicbom = true;
- cpu->cfg.cbom_blocksize = 64;
- cpu->cfg.cboz_blocksize = 64;
- cpu->cfg.ext_zicboz = true;
- cpu->cfg.ext_smaia = true;
- cpu->cfg.ext_ssaia = true;
- cpu->cfg.ext_sscofpmf = true;
- cpu->cfg.ext_sstc = true;
- cpu->cfg.ext_svinval = true;
- cpu->cfg.ext_svnapot = true;
- cpu->cfg.ext_svpbmt = true;
- cpu->cfg.ext_smstateen = true;
- cpu->cfg.ext_zba = true;
- cpu->cfg.ext_zbb = true;
- cpu->cfg.ext_zbc = true;
- cpu->cfg.ext_zbs = true;
- cpu->cfg.ext_XVentanaCondOps = true;
-
- cpu->cfg.mvendorid = VEYRON_V1_MVENDORID;
- cpu->cfg.marchid = VEYRON_V1_MARCHID;
- cpu->cfg.mimpid = VEYRON_V1_MIMPID;
-
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_SV48);
-#endif
-}
static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
{
@@ -3088,7 +3049,41 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.max_satp_mode = VM_1_10_SV57,
),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_VEYRON_V1, TYPE_RISCV_VENDOR_CPU,
+ .misa_mxl_max = MXL_RV64,
+ .misa_ext = RVG | RVC | RVS | RVU | RVH,
+ .priv_spec = PRIV_VERSION_1_12_0,
+
+ /* ISA extensions */
+ .cfg.mmu = true,
+ .cfg.ext_zifencei = true,
+ .cfg.ext_zicsr = true,
+ .cfg.pmp = true,
+ .cfg.ext_zicbom = true,
+ .cfg.cbom_blocksize = 64,
+ .cfg.cboz_blocksize = 64,
+ .cfg.ext_zicboz = true,
+ .cfg.ext_smaia = true,
+ .cfg.ext_ssaia = true,
+ .cfg.ext_sscofpmf = true,
+ .cfg.ext_sstc = true,
+ .cfg.ext_svinval = true,
+ .cfg.ext_svnapot = true,
+ .cfg.ext_svpbmt = true,
+ .cfg.ext_smstateen = true,
+ .cfg.ext_zba = true,
+ .cfg.ext_zbb = true,
+ .cfg.ext_zbc = true,
+ .cfg.ext_zbs = true,
+ .cfg.ext_XVentanaCondOps = true,
+
+ .cfg.mvendorid = VEYRON_V1_MVENDORID,
+ .cfg.marchid = VEYRON_V1_MARCHID,
+ .cfg.mimpid = VEYRON_V1_MIMPID,
+
+ .cfg.max_satp_mode = VM_1_10_SV48,
+ ),
+
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
MXL_RV64, rv64_xiangshan_nanhu_cpu_init),
#ifdef CONFIG_TCG
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 21/22] target/riscv: convert Xiangshan Nanhu to RISCVCPUDef
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (19 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 20/22] target/riscv: convert Ventana V1 " Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-02-28 10:27 ` [PATCH 22/22] target/riscv: remove .instance_post_init Paolo Bonzini
2025-04-17 13:40 ` [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
22 siblings, 0 replies; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 77 ++++++++++++++--------------------------------
1 file changed, 23 insertions(+), 54 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a6c97a43799..ceda1a6e630 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -438,16 +438,6 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit)
g_assert_not_reached();
}
-static void set_satp_mode_max_supported(RISCVCPU *cpu,
- int satp_mode)
-{
- bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
- const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
-
- assert(valid_vm[satp_mode]);
- cpu->cfg.max_satp_mode = satp_mode;
-}
-
static bool get_satp_mode_supported(RISCVCPU *cpu, uint16_t *supported)
{
bool rv32 = riscv_cpu_is_32bit(cpu);
@@ -496,38 +486,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list)
}
#endif
-#if defined(TARGET_RISCV64)
-
-static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVG | RVC | RVB | RVS | RVU);
- env->priv_ver = PRIV_VERSION_1_12_0;
-
- /* Enable ISA extensions */
- cpu->cfg.ext_zbc = true;
- cpu->cfg.ext_zbkb = true;
- cpu->cfg.ext_zbkc = true;
- cpu->cfg.ext_zbkx = true;
- cpu->cfg.ext_zknd = true;
- cpu->cfg.ext_zkne = true;
- cpu->cfg.ext_zknh = true;
- cpu->cfg.ext_zksed = true;
- cpu->cfg.ext_zksh = true;
- cpu->cfg.ext_svinval = true;
-
- cpu->cfg.mmu = true;
- cpu->cfg.pmp = true;
-
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_SV39);
-#endif
-}
-
-#endif /* !TARGET_RISCV64 */
-
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
@@ -2777,16 +2735,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
}
#endif
-#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max_, initfn) \
- { \
- .name = (type_name), \
- .parent = TYPE_RISCV_VENDOR_CPU, \
- .instance_init = (initfn), \
- .class_data = (void*) &((const RISCVCPUDef) { \
- .misa_mxl_max = (misa_mxl_max_), \
- }), \
- }
-
#define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \
{ \
.name = (type_name), \
@@ -3084,8 +3032,29 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.max_satp_mode = VM_1_10_SV48,
),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
- MXL_RV64, rv64_xiangshan_nanhu_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, TYPE_RISCV_VENDOR_CPU,
+ .misa_mxl_max = MXL_RV64,
+ .misa_ext = RVG | RVC | RVB | RVS | RVU,
+ .priv_spec = PRIV_VERSION_1_12_0,
+
+ /* ISA extensions */
+ .cfg.ext_zbc = true,
+ .cfg.ext_zbkb = true,
+ .cfg.ext_zbkc = true,
+ .cfg.ext_zbkx = true,
+ .cfg.ext_zknd = true,
+ .cfg.ext_zkne = true,
+ .cfg.ext_zknh = true,
+ .cfg.ext_zksed = true,
+ .cfg.ext_zksh = true,
+ .cfg.ext_svinval = true,
+
+ .cfg.mmu = true,
+ .cfg.pmp = true,
+
+ .cfg.max_satp_mode = VM_1_10_SV39,
+ ),
+
#ifdef CONFIG_TCG
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
.cfg.max_satp_mode = VM_1_10_SV57,
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH 22/22] target/riscv: remove .instance_post_init
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (20 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 21/22] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
@ 2025-02-28 10:27 ` Paolo Bonzini
2025-04-17 13:40 ` [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
22 siblings, 0 replies; 31+ messages in thread
From: Paolo Bonzini @ 2025-02-28 10:27 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair.francis
Unlike other uses of .instance_post_init, accel_cpu_instance_init()
*registers* properties, and therefore must be run before
device_post_init() which sets them to their values from -global.
In order to move all registration of properties to .instance_init,
call accel_cpu_instance_init() at the end of riscv_cpu_init().
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ceda1a6e630..e261b24a21a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1079,11 +1079,6 @@ static bool riscv_cpu_is_dynamic(Object *cpu_obj)
return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
}
-static void riscv_cpu_post_init(Object *obj)
-{
- accel_cpu_instance_init(CPU(obj));
-}
-
static void riscv_cpu_init(Object *obj)
{
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj);
@@ -1139,6 +1134,8 @@ static void riscv_cpu_init(Object *obj)
riscv_register_custom_csrs(cpu, mcc->def->custom_csrs);
}
#endif
+
+ accel_cpu_instance_init(CPU(obj));
}
typedef struct misa_ext_info {
@@ -2769,7 +2766,6 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.instance_size = sizeof(RISCVCPU),
.instance_align = __alignof(RISCVCPU),
.instance_init = riscv_cpu_init,
- .instance_post_init = riscv_cpu_post_init,
.abstract = true,
.class_size = sizeof(RISCVCPUClass),
.class_init = riscv_cpu_common_class_init,
--
2.48.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH 03/22] target/riscv: introduce RISCVCPUDef
2025-02-28 10:27 ` [PATCH 03/22] target/riscv: introduce RISCVCPUDef Paolo Bonzini
@ 2025-02-28 17:19 ` Richard Henderson
0 siblings, 0 replies; 31+ messages in thread
From: Richard Henderson @ 2025-02-28 17:19 UTC (permalink / raw)
To: qemu-devel
On 2/28/25 02:27, Paolo Bonzini wrote:
> - .class_data = GUINT_TO_POINTER(misa_mxl_max) \
> + .class_data = (void*) &((const RISCVCPUDef) { \
> + .misa_mxl_max = (misa_mxl_max_), \
> + }), \
Drop the extra () and unnecessary cast.
.class_data = &(const RISCVCPUDef) {
...
},
With that,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 01/22] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL
2025-02-28 10:27 ` [PATCH 01/22] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Paolo Bonzini
@ 2025-03-06 0:46 ` Alistair Francis
0 siblings, 0 replies; 31+ messages in thread
From: Alistair Francis @ 2025-03-06 0:46 UTC (permalink / raw)
To: Paolo Bonzini
Cc: qemu-devel, alistair.francis, Philippe Mathieu-Daudé,
Richard Henderson
On Fri, Feb 28, 2025 at 8:31 PM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Link: https://lore.kernel.org/r/20250212213249.45574-7-philmd@linaro.org
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 2 +-
> target/riscv/cpu.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index df7a05e7d15..3041a4be5c9 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -543,7 +543,7 @@ struct RISCVCPUClass {
>
> DeviceRealize parent_realize;
> ResettablePhases parent_phases;
> - uint32_t misa_mxl_max; /* max mxl for this cpu */
> + RISCVMXL misa_mxl_max; /* max mxl for this cpu */
> };
>
> static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 244e44ce410..85dc2fe3bec 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2961,7 +2961,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> {
> RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
>
> - mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
> + mcc->misa_mxl_max = (RISCVMXL)(uintptr_t)data;
> riscv_cpu_validate_misa_mxl(mcc);
> }
>
> --
> 2.48.1
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 02/22] target/riscv: Convert misa_mxl_max using GLib macros
2025-02-28 10:27 ` [PATCH 02/22] target/riscv: Convert misa_mxl_max using GLib macros Paolo Bonzini
@ 2025-03-06 0:47 ` Alistair Francis
0 siblings, 0 replies; 31+ messages in thread
From: Alistair Francis @ 2025-03-06 0:47 UTC (permalink / raw)
To: Paolo Bonzini
Cc: qemu-devel, alistair.francis, Philippe Mathieu-Daudé,
Richard Henderson
On Fri, Feb 28, 2025 at 8:30 PM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
>
> Use GLib conversion macros to pass misa_mxl_max as
> riscv_cpu_class_init() class data.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Link: https://lore.kernel.org/r/20250212213249.45574-8-philmd@linaro.org
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 85dc2fe3bec..f05b72ac873 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2961,7 +2961,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> {
> RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
>
> - mcc->misa_mxl_max = (RISCVMXL)(uintptr_t)data;
> + mcc->misa_mxl_max = (RISCVMXL)GPOINTER_TO_UINT(data);
> riscv_cpu_validate_misa_mxl(mcc);
> }
>
> @@ -3063,7 +3063,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
> .parent = TYPE_RISCV_DYNAMIC_CPU, \
> .instance_init = (initfn), \
> .class_init = riscv_cpu_class_init, \
> - .class_data = (void *)(misa_mxl_max) \
> + .class_data = GUINT_TO_POINTER(misa_mxl_max) \
> }
>
> #define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \
> @@ -3072,7 +3072,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
> .parent = TYPE_RISCV_VENDOR_CPU, \
> .instance_init = (initfn), \
> .class_init = riscv_cpu_class_init, \
> - .class_data = (void *)(misa_mxl_max) \
> + .class_data = GUINT_TO_POINTER(misa_mxl_max) \
> }
>
> #define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \
> @@ -3081,7 +3081,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
> .parent = TYPE_RISCV_BARE_CPU, \
> .instance_init = (initfn), \
> .class_init = riscv_cpu_class_init, \
> - .class_data = (void *)(misa_mxl_max) \
> + .class_data = GUINT_TO_POINTER(misa_mxl_max) \
> }
>
> #define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \
> @@ -3090,7 +3090,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
> .parent = TYPE_RISCV_BARE_CPU, \
> .instance_init = (initfn), \
> .class_init = riscv_cpu_class_init, \
> - .class_data = (void *)(misa_mxl_max) \
> + .class_data = GUINT_TO_POINTER(misa_mxl_max) \
> }
>
> static const TypeInfo riscv_cpu_type_infos[] = {
> --
> 2.48.1
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 04/22] target/riscv: store RISCVCPUDef struct directly in the class
2025-02-28 10:27 ` [PATCH 04/22] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
@ 2025-03-06 0:50 ` Alistair Francis
0 siblings, 0 replies; 31+ messages in thread
From: Alistair Francis @ 2025-03-06 0:50 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel, alistair.francis
On Fri, Feb 28, 2025 at 8:31 PM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> Prepare for adding more fields to RISCVCPUDef and reading them in
> riscv_cpu_init: instead of storing the misa_mxl_max field in
> RISCVCPUClass, ensure that there's always a valid RISCVCPUDef struct
> and go through it.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 2 +-
> hw/riscv/boot.c | 2 +-
> target/riscv/cpu.c | 23 ++++++++++++++++++-----
> target/riscv/gdbstub.c | 6 +++---
> target/riscv/kvm/kvm-cpu.c | 21 +++++++++------------
> target/riscv/machine.c | 6 +++---
> target/riscv/tcg/tcg-cpu.c | 10 +++++-----
> target/riscv/translate.c | 2 +-
> 8 files changed, 41 insertions(+), 31 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 743afeb1655..a038122f80c 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -547,7 +547,7 @@ struct RISCVCPUClass {
>
> DeviceRealize parent_realize;
> ResettablePhases parent_phases;
> - RISCVMXL misa_mxl_max; /* max mxl for this cpu */
> + RISCVCPUDef *def;
> };
>
> static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index c309441b7d8..13728e137c4 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -37,7 +37,7 @@
> bool riscv_is_32bit(RISCVHartArrayState *harts)
> {
> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]);
> - return mcc->misa_mxl_max == MXL_RV32;
> + return mcc->def->misa_mxl_max == MXL_RV32;
> }
>
> /*
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a71d806e35f..51acce07752 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -354,7 +354,7 @@ void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)
>
> int riscv_cpu_max_xlen(RISCVCPUClass *mcc)
> {
> - return 16 << mcc->misa_mxl_max;
> + return 16 << mcc->def->misa_mxl_max;
> }
>
> #ifndef CONFIG_USER_ONLY
> @@ -1054,7 +1054,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
> mcc->parent_phases.hold(obj, type);
> }
> #ifndef CONFIG_USER_ONLY
> - env->misa_mxl = mcc->misa_mxl_max;
> + env->misa_mxl = mcc->def->misa_mxl_max;
> env->priv = PRV_M;
> env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
> if (env->misa_mxl > MXL_RV32) {
> @@ -1447,7 +1447,7 @@ static void riscv_cpu_init(Object *obj)
> RISCVCPU *cpu = RISCV_CPU(obj);
> CPURISCVState *env = &cpu->env;
>
> - env->misa_mxl = mcc->misa_mxl_max;
> + env->misa_mxl = mcc->def->misa_mxl_max;
>
> #ifndef CONFIG_USER_ONLY
> qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
> @@ -1544,7 +1544,7 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
> CPUClass *cc = CPU_CLASS(mcc);
>
> /* Validate that MISA_MXL is set properly. */
> - switch (mcc->misa_mxl_max) {
> + switch (mcc->def->misa_mxl_max) {
> #ifdef TARGET_RISCV64
> case MXL_RV64:
> case MXL_RV128:
> @@ -2957,12 +2957,24 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data)
> device_class_set_props(dc, riscv_cpu_properties);
> }
>
> +static void riscv_cpu_class_base_init(ObjectClass *c, void *data)
> +{
> + RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> + RISCVCPUClass *pcc = RISCV_CPU_CLASS(object_class_get_parent(c));
> +
> + if (pcc->def) {
> + mcc->def = g_memdup2(pcc->def, sizeof(*pcc->def));
> + } else {
> + mcc->def = g_new0(RISCVCPUDef, 1);
> + }
> +}
> +
> static void riscv_cpu_class_init(ObjectClass *c, void *data)
> {
> RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> const RISCVCPUDef *def = data;
>
> - mcc->misa_mxl_max = def->misa_mxl_max;
> + mcc->def->misa_mxl_max = def->misa_mxl_max;
> riscv_cpu_validate_misa_mxl(mcc);
> }
>
> @@ -3113,6 +3125,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .abstract = true,
> .class_size = sizeof(RISCVCPUClass),
> .class_init = riscv_cpu_common_class_init,
> + .class_base_init = riscv_cpu_class_base_init,
> },
> {
> .name = TYPE_RISCV_DYNAMIC_CPU,
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 18e88f416af..1934f919c01 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -62,7 +62,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
> return 0;
> }
>
> - switch (mcc->misa_mxl_max) {
> + switch (mcc->def->misa_mxl_max) {
> case MXL_RV32:
> return gdb_get_reg32(mem_buf, tmp);
> case MXL_RV64:
> @@ -82,7 +82,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> int length = 0;
> target_ulong tmp;
>
> - switch (mcc->misa_mxl_max) {
> + switch (mcc->def->misa_mxl_max) {
> case MXL_RV32:
> tmp = (int32_t)ldl_p(mem_buf);
> length = 4;
> @@ -359,7 +359,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
> ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
> 0);
> }
> - switch (mcc->misa_mxl_max) {
> + switch (mcc->def->misa_mxl_max) {
> case MXL_RV32:
> gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
> riscv_gdb_set_virtual,
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index 23ce7793594..f3ec4f33931 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -1985,22 +1985,19 @@ static void kvm_cpu_accel_register_types(void)
> }
> type_init(kvm_cpu_accel_register_types);
>
> -static void riscv_host_cpu_class_init(ObjectClass *c, void *data)
> -{
> - RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> -
> -#if defined(TARGET_RISCV32)
> - mcc->misa_mxl_max = MXL_RV32;
> -#elif defined(TARGET_RISCV64)
> - mcc->misa_mxl_max = MXL_RV64;
> -#endif
> -}
> -
> static const TypeInfo riscv_kvm_cpu_type_infos[] = {
> {
> .name = TYPE_RISCV_CPU_HOST,
> .parent = TYPE_RISCV_CPU,
> - .class_init = riscv_host_cpu_class_init,
> +#if defined(TARGET_RISCV32)
> + .class_data = &((const RISCVCPUDef) {
> + .misa_mxl_max = MXL_RV32,
> + },
> +#elif defined(TARGET_RISCV64)
> + .class_data = &((const RISCVCPUDef) {
> + .misa_mxl_max = MXL_RV64,
> + },
> +#endif
> }
> };
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index c3d8e7c4005..98d20afd04d 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -170,7 +170,7 @@ static bool rv128_needed(void *opaque)
> {
> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(opaque);
>
> - return mcc->misa_mxl_max == MXL_RV128;
> + return mcc->def->misa_mxl_max == MXL_RV128;
> }
>
> static const VMStateDescription vmstate_rv128 = {
> @@ -383,8 +383,8 @@ static bool riscv_validate_misa_mxl(void *opaque, int version_id)
> uint32_t misa_mxl_saved = env->misa_mxl;
>
> /* Preserve misa_mxl even if the migration stream corrupted it */
> - env->misa_mxl = mcc->misa_mxl_max;
> - return misa_mxl_saved == mcc->misa_mxl_max;
> + env->misa_mxl = mcc->def->misa_mxl_max;
> + return misa_mxl_saved == mcc->def->misa_mxl_max;
> }
>
> const VMStateDescription vmstate_riscv_cpu = {
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index e5e01715f10..f434b2448db 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -579,7 +579,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> return;
> }
>
> - if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
> + if (mcc->def->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
> error_setg(errp, "Zcf extension is only relevant to RV32");
> return;
> }
> @@ -676,7 +676,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> return;
> }
>
> - if (mcc->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) {
> + if (mcc->def->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) {
> error_setg(errp, "svukte is not supported for RV32");
> return;
> }
> @@ -891,7 +891,7 @@ static void cpu_enable_zc_implied_rules(RISCVCPU *cpu)
> cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
> cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
>
> - if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
> + if (riscv_has_ext(env, RVF) && mcc->def->misa_mxl_max == MXL_RV32) {
> cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
> }
> }
> @@ -900,7 +900,7 @@ static void cpu_enable_zc_implied_rules(RISCVCPU *cpu)
> if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
> cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
>
> - if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
> + if (riscv_has_ext(env, RVF) && mcc->def->misa_mxl_max == MXL_RV32) {
> cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
> }
>
> @@ -1024,7 +1024,7 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
> return false;
> }
>
> - if (mcc->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
> + if (mcc->def->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
> /* Missing 128-bit aligned atomics */
> error_setg(errp,
> "128-bit RISC-V currently does not work with Multi "
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 698b74f7a8f..782e724a648 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1234,7 +1234,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;
> ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO);
> ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
> - ctx->misa_mxl_max = mcc->misa_mxl_max;
> + ctx->misa_mxl_max = mcc->def->misa_mxl_max;
> ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
> ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
> ctx->cs = cs;
> --
> 2.48.1
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 05/22] target/riscv: merge riscv_cpu_class_init with the class_base function
2025-02-28 10:27 ` [PATCH 05/22] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
@ 2025-03-06 0:52 ` Alistair Francis
0 siblings, 0 replies; 31+ messages in thread
From: Alistair Francis @ 2025-03-06 0:52 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel, alistair.francis
On Fri, Feb 28, 2025 at 8:33 PM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> Since all TYPE_RISCV_CPU subclasses support a class_data of type
> RISCVCPUDef, process it even before calling the .class_init function
> for the subclasses.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 21 ++++++++++-----------
> 1 file changed, 10 insertions(+), 11 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 51acce07752..91dd63edc9f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2967,15 +2967,18 @@ static void riscv_cpu_class_base_init(ObjectClass *c, void *data)
> } else {
> mcc->def = g_new0(RISCVCPUDef, 1);
> }
> -}
>
> -static void riscv_cpu_class_init(ObjectClass *c, void *data)
> -{
> - RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> - const RISCVCPUDef *def = data;
> + if (data) {
> + const RISCVCPUDef *def = data;
> + if (def->misa_mxl_max) {
> + assert(def->misa_mxl_max <= MXL_RV128);
> + mcc->def->misa_mxl_max = def->misa_mxl_max;
> + }
> + }
>
> - mcc->def->misa_mxl_max = def->misa_mxl_max;
> - riscv_cpu_validate_misa_mxl(mcc);
> + if (!object_class_is_abstract(c)) {
> + riscv_cpu_validate_misa_mxl(mcc);
> + }
> }
>
> static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
> @@ -3075,7 +3078,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
> .name = (type_name), \
> .parent = TYPE_RISCV_DYNAMIC_CPU, \
> .instance_init = (initfn), \
> - .class_init = riscv_cpu_class_init, \
> .class_data = (void*) &((const RISCVCPUDef) { \
> .misa_mxl_max = (misa_mxl_max_), \
> }), \
> @@ -3086,7 +3088,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
> .name = (type_name), \
> .parent = TYPE_RISCV_VENDOR_CPU, \
> .instance_init = (initfn), \
> - .class_init = riscv_cpu_class_init, \
> .class_data = (void*) &((const RISCVCPUDef) { \
> .misa_mxl_max = (misa_mxl_max_), \
> }), \
> @@ -3097,7 +3098,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
> .name = (type_name), \
> .parent = TYPE_RISCV_BARE_CPU, \
> .instance_init = (initfn), \
> - .class_init = riscv_cpu_class_init, \
> .class_data = (void*) &((const RISCVCPUDef) { \
> .misa_mxl_max = (misa_mxl_max_), \
> }), \
> @@ -3108,7 +3108,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
> .name = (type_name), \
> .parent = TYPE_RISCV_BARE_CPU, \
> .instance_init = (initfn), \
> - .class_init = riscv_cpu_class_init, \
> .class_data = (void*) &((const RISCVCPUDef) { \
> .misa_mxl_max = (misa_mxl_max_), \
> }), \
> --
> 2.48.1
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 06/22] target/riscv: move RISCVCPUConfig fields to a header file
2025-02-28 10:27 ` [PATCH 06/22] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
@ 2025-03-06 0:53 ` Alistair Francis
0 siblings, 0 replies; 31+ messages in thread
From: Alistair Francis @ 2025-03-06 0:53 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel, alistair.francis
On Fri, Feb 28, 2025 at 8:31 PM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> To support merging a subclass's RISCVCPUDef into the superclass, a list
> of all the CPU features is needed. Put them into a header file that
> can be included multiple times, expanding the macros BOOL_FIELD and
> TYPE_FIELD to different operations.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_cfg.h | 160 +---------------------------
> target/riscv/cpu_cfg_fields.h.inc | 167 ++++++++++++++++++++++++++++++
> 2 files changed, 170 insertions(+), 157 deletions(-)
> create mode 100644 target/riscv/cpu_cfg_fields.h.inc
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 7b7067d5bee..e9bf75730a6 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -22,163 +22,9 @@
> #define RISCV_CPU_CFG_H
>
> struct RISCVCPUConfig {
> - bool ext_zba;
> - bool ext_zbb;
> - bool ext_zbc;
> - bool ext_zbkb;
> - bool ext_zbkc;
> - bool ext_zbkx;
> - bool ext_zbs;
> - bool ext_zca;
> - bool ext_zcb;
> - bool ext_zcd;
> - bool ext_zce;
> - bool ext_zcf;
> - bool ext_zcmp;
> - bool ext_zcmt;
> - bool ext_zk;
> - bool ext_zkn;
> - bool ext_zknd;
> - bool ext_zkne;
> - bool ext_zknh;
> - bool ext_zkr;
> - bool ext_zks;
> - bool ext_zksed;
> - bool ext_zksh;
> - bool ext_zkt;
> - bool ext_zifencei;
> - bool ext_zicntr;
> - bool ext_zicsr;
> - bool ext_zicbom;
> - bool ext_zicbop;
> - bool ext_zicboz;
> - bool ext_zicfilp;
> - bool ext_zicfiss;
> - bool ext_zicond;
> - bool ext_zihintntl;
> - bool ext_zihintpause;
> - bool ext_zihpm;
> - bool ext_zimop;
> - bool ext_zcmop;
> - bool ext_ztso;
> - bool ext_smstateen;
> - bool ext_sstc;
> - bool ext_smcdeleg;
> - bool ext_ssccfg;
> - bool ext_smcntrpmf;
> - bool ext_smcsrind;
> - bool ext_sscsrind;
> - bool ext_ssdbltrp;
> - bool ext_smdbltrp;
> - bool ext_svadu;
> - bool ext_svinval;
> - bool ext_svnapot;
> - bool ext_svpbmt;
> - bool ext_svvptc;
> - bool ext_svukte;
> - bool ext_zdinx;
> - bool ext_zaamo;
> - bool ext_zacas;
> - bool ext_zama16b;
> - bool ext_zabha;
> - bool ext_zalrsc;
> - bool ext_zawrs;
> - bool ext_zfa;
> - bool ext_zfbfmin;
> - bool ext_zfh;
> - bool ext_zfhmin;
> - bool ext_zfinx;
> - bool ext_zhinx;
> - bool ext_zhinxmin;
> - bool ext_zve32f;
> - bool ext_zve32x;
> - bool ext_zve64f;
> - bool ext_zve64d;
> - bool ext_zve64x;
> - bool ext_zvbb;
> - bool ext_zvbc;
> - bool ext_zvkb;
> - bool ext_zvkg;
> - bool ext_zvkned;
> - bool ext_zvknha;
> - bool ext_zvknhb;
> - bool ext_zvksed;
> - bool ext_zvksh;
> - bool ext_zvkt;
> - bool ext_zvkn;
> - bool ext_zvknc;
> - bool ext_zvkng;
> - bool ext_zvks;
> - bool ext_zvksc;
> - bool ext_zvksg;
> - bool ext_zmmul;
> - bool ext_zvfbfmin;
> - bool ext_zvfbfwma;
> - bool ext_zvfh;
> - bool ext_zvfhmin;
> - bool ext_smaia;
> - bool ext_ssaia;
> - bool ext_sscofpmf;
> - bool ext_smepmp;
> - bool ext_smrnmi;
> - bool ext_ssnpm;
> - bool ext_smnpm;
> - bool ext_smmpm;
> - bool ext_sspm;
> - bool ext_supm;
> - bool rvv_ta_all_1s;
> - bool rvv_ma_all_1s;
> - bool rvv_vl_half_avl;
> -
> - uint32_t mvendorid;
> - uint64_t marchid;
> - uint64_t mimpid;
> -
> - /* Named features */
> - bool ext_svade;
> - bool ext_zic64b;
> - bool ext_ssstateen;
> - bool ext_sha;
> -
> - /*
> - * Always 'true' booleans for named features
> - * TCG always implement/can't be user disabled,
> - * based on spec version.
> - */
> - bool has_priv_1_13;
> - bool has_priv_1_12;
> - bool has_priv_1_11;
> -
> - /* Vendor-specific custom extensions */
> - bool ext_xtheadba;
> - bool ext_xtheadbb;
> - bool ext_xtheadbs;
> - bool ext_xtheadcmo;
> - bool ext_xtheadcondmov;
> - bool ext_xtheadfmemidx;
> - bool ext_xtheadfmv;
> - bool ext_xtheadmac;
> - bool ext_xtheadmemidx;
> - bool ext_xtheadmempair;
> - bool ext_xtheadsync;
> - bool ext_XVentanaCondOps;
> -
> - uint32_t pmu_mask;
> - uint16_t vlenb;
> - uint16_t elen;
> - uint16_t cbom_blocksize;
> - uint16_t cbop_blocksize;
> - uint16_t cboz_blocksize;
> - bool mmu;
> - bool pmp;
> - bool debug;
> - bool misa_w;
> -
> - bool short_isa_string;
> -
> -#ifndef CONFIG_USER_ONLY
> - int8_t max_satp_mode;
> -#endif
> +#define BOOL_FIELD(x) bool x;
> +#define TYPED_FIELD(type, x) type x;
> +#include "cpu_cfg_fields.h.inc"
> };
>
> typedef struct RISCVCPUConfig RISCVCPUConfig;
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> new file mode 100644
> index 00000000000..a42f298017f
> --- /dev/null
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -0,0 +1,167 @@
> +/*
> + * Required definitions before including this file:
> + *
> + * #define BOOL_FIELD(x)
> + * #define TYPED_FIELD(type, x)
> + */
> +
> +BOOL_FIELD(ext_zba)
> +BOOL_FIELD(ext_zbb)
> +BOOL_FIELD(ext_zbc)
> +BOOL_FIELD(ext_zbkb)
> +BOOL_FIELD(ext_zbkc)
> +BOOL_FIELD(ext_zbkx)
> +BOOL_FIELD(ext_zbs)
> +BOOL_FIELD(ext_zca)
> +BOOL_FIELD(ext_zcb)
> +BOOL_FIELD(ext_zcd)
> +BOOL_FIELD(ext_zce)
> +BOOL_FIELD(ext_zcf)
> +BOOL_FIELD(ext_zcmp)
> +BOOL_FIELD(ext_zcmt)
> +BOOL_FIELD(ext_zk)
> +BOOL_FIELD(ext_zkn)
> +BOOL_FIELD(ext_zknd)
> +BOOL_FIELD(ext_zkne)
> +BOOL_FIELD(ext_zknh)
> +BOOL_FIELD(ext_zkr)
> +BOOL_FIELD(ext_zks)
> +BOOL_FIELD(ext_zksed)
> +BOOL_FIELD(ext_zksh)
> +BOOL_FIELD(ext_zkt)
> +BOOL_FIELD(ext_zifencei)
> +BOOL_FIELD(ext_zicntr)
> +BOOL_FIELD(ext_zicsr)
> +BOOL_FIELD(ext_zicbom)
> +BOOL_FIELD(ext_zicbop)
> +BOOL_FIELD(ext_zicboz)
> +BOOL_FIELD(ext_zicfilp)
> +BOOL_FIELD(ext_zicfiss)
> +BOOL_FIELD(ext_zicond)
> +BOOL_FIELD(ext_zihintntl)
> +BOOL_FIELD(ext_zihintpause)
> +BOOL_FIELD(ext_zihpm)
> +BOOL_FIELD(ext_zimop)
> +BOOL_FIELD(ext_zcmop)
> +BOOL_FIELD(ext_ztso)
> +BOOL_FIELD(ext_smstateen)
> +BOOL_FIELD(ext_sstc)
> +BOOL_FIELD(ext_smcdeleg)
> +BOOL_FIELD(ext_ssccfg)
> +BOOL_FIELD(ext_smcntrpmf)
> +BOOL_FIELD(ext_smcsrind)
> +BOOL_FIELD(ext_sscsrind)
> +BOOL_FIELD(ext_ssdbltrp)
> +BOOL_FIELD(ext_smdbltrp)
> +BOOL_FIELD(ext_svadu)
> +BOOL_FIELD(ext_svinval)
> +BOOL_FIELD(ext_svnapot)
> +BOOL_FIELD(ext_svpbmt)
> +BOOL_FIELD(ext_svvptc)
> +BOOL_FIELD(ext_svukte)
> +BOOL_FIELD(ext_zdinx)
> +BOOL_FIELD(ext_zaamo)
> +BOOL_FIELD(ext_zacas)
> +BOOL_FIELD(ext_zama16b)
> +BOOL_FIELD(ext_zabha)
> +BOOL_FIELD(ext_zalrsc)
> +BOOL_FIELD(ext_zawrs)
> +BOOL_FIELD(ext_zfa)
> +BOOL_FIELD(ext_zfbfmin)
> +BOOL_FIELD(ext_zfh)
> +BOOL_FIELD(ext_zfhmin)
> +BOOL_FIELD(ext_zfinx)
> +BOOL_FIELD(ext_zhinx)
> +BOOL_FIELD(ext_zhinxmin)
> +BOOL_FIELD(ext_zve32f)
> +BOOL_FIELD(ext_zve32x)
> +BOOL_FIELD(ext_zve64f)
> +BOOL_FIELD(ext_zve64d)
> +BOOL_FIELD(ext_zve64x)
> +BOOL_FIELD(ext_zvbb)
> +BOOL_FIELD(ext_zvbc)
> +BOOL_FIELD(ext_zvkb)
> +BOOL_FIELD(ext_zvkg)
> +BOOL_FIELD(ext_zvkned)
> +BOOL_FIELD(ext_zvknha)
> +BOOL_FIELD(ext_zvknhb)
> +BOOL_FIELD(ext_zvksed)
> +BOOL_FIELD(ext_zvksh)
> +BOOL_FIELD(ext_zvkt)
> +BOOL_FIELD(ext_zvkn)
> +BOOL_FIELD(ext_zvknc)
> +BOOL_FIELD(ext_zvkng)
> +BOOL_FIELD(ext_zvks)
> +BOOL_FIELD(ext_zvksc)
> +BOOL_FIELD(ext_zvksg)
> +BOOL_FIELD(ext_zmmul)
> +BOOL_FIELD(ext_zvfbfmin)
> +BOOL_FIELD(ext_zvfbfwma)
> +BOOL_FIELD(ext_zvfh)
> +BOOL_FIELD(ext_zvfhmin)
> +BOOL_FIELD(ext_smaia)
> +BOOL_FIELD(ext_ssaia)
> +BOOL_FIELD(ext_sscofpmf)
> +BOOL_FIELD(ext_smepmp)
> +BOOL_FIELD(ext_smrnmi)
> +BOOL_FIELD(ext_ssnpm)
> +BOOL_FIELD(ext_smnpm)
> +BOOL_FIELD(ext_smmpm)
> +BOOL_FIELD(ext_sspm)
> +BOOL_FIELD(ext_supm)
> +BOOL_FIELD(rvv_ta_all_1s)
> +BOOL_FIELD(rvv_ma_all_1s)
> +BOOL_FIELD(rvv_vl_half_avl)
> +/* Named features */
> +BOOL_FIELD(ext_svade)
> +BOOL_FIELD(ext_zic64b)
> +BOOL_FIELD(ext_ssstateen)
> +BOOL_FIELD(ext_sha)
> +
> +/*
> + * Always 'true' booleans for named features
> + * TCG always implement/can't be user disabled,
> + * based on spec version.
> + */
> +BOOL_FIELD(has_priv_1_13)
> +BOOL_FIELD(has_priv_1_12)
> +BOOL_FIELD(has_priv_1_11)
> +
> +/* Vendor-specific custom extensions */
> +BOOL_FIELD(ext_xtheadba)
> +BOOL_FIELD(ext_xtheadbb)
> +BOOL_FIELD(ext_xtheadbs)
> +BOOL_FIELD(ext_xtheadcmo)
> +BOOL_FIELD(ext_xtheadcondmov)
> +BOOL_FIELD(ext_xtheadfmemidx)
> +BOOL_FIELD(ext_xtheadfmv)
> +BOOL_FIELD(ext_xtheadmac)
> +BOOL_FIELD(ext_xtheadmemidx)
> +BOOL_FIELD(ext_xtheadmempair)
> +BOOL_FIELD(ext_xtheadsync)
> +BOOL_FIELD(ext_XVentanaCondOps)
> +
> +BOOL_FIELD(mmu)
> +BOOL_FIELD(pmp)
> +BOOL_FIELD(debug)
> +BOOL_FIELD(misa_w)
> +
> +BOOL_FIELD(short_isa_string)
> +
> +TYPED_FIELD(uint32_t, mvendorid)
> +TYPED_FIELD(uint64_t, marchid)
> +TYPED_FIELD(uint64_t, mimpid)
> +
> +TYPED_FIELD(uint32_t, pmu_mask)
> +TYPED_FIELD(uint16_t, vlenb)
> +TYPED_FIELD(uint16_t, elen)
> +TYPED_FIELD(uint16_t, cbom_blocksize)
> +TYPED_FIELD(uint16_t, cbop_blocksize)
> +TYPED_FIELD(uint16_t, cboz_blocksize)
> +
> +#ifndef CONFIG_USER_ONLY
> +TYPED_FIELD(int8_t, max_satp_mode)
> +#endif
> +
> +#undef BOOL_FIELD
> +#undef TYPED_FIELD
> --
> 2.48.1
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 00/22] target/riscv: declarative CPU definitions
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
` (21 preceding siblings ...)
2025-02-28 10:27 ` [PATCH 22/22] target/riscv: remove .instance_post_init Paolo Bonzini
@ 2025-04-17 13:40 ` Paolo Bonzini
2025-04-24 10:37 ` Alistair Francis
22 siblings, 1 reply; 31+ messages in thread
From: Paolo Bonzini @ 2025-04-17 13:40 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis
[-- Attachment #1: Type: text/plain, Size: 4059 bytes --]
Hi Alistair,
sorry for the stupid question—I am not sure whether you are going to give
reviewed-by to the remaining patches, and also whether you would like me to
submit the PR for this or not.
Thanks in advance
Paolo
Il ven 28 feb 2025, 11:27 Paolo Bonzini <pbonzini@redhat.com> ha scritto:
> As in v1, what I really wanted to achieve was removing RISC-V's
> use of .instance_post_init; that's because RISC-V operate with an
> opposite conception of .instance_post_init compared to everyone
> else: RISC-V wants to register properties there, whereas x86 and
> hw/pci-bridge/pcie_root_port.c want to set them. While it's possible
> to move RISC-V's code to instance_init, the others have to run after
> global properties have been set by device_post_init().
>
> The way to get there is to make CPU definitions entirely declarative.
> Previously, multiple instance_init functions each override the properties
> that were set by the superclass, and the code used a mix of subclassing
> and direct invocation of other functions. Now, instead, after .class_init
> all the settings for each model are available in a RISCVCPUDef struct,
> and the result is copied into the RISCVCPU at .instance_init time.
> This is done with a single function that starts from the parent's
> RISCVCPUDef and applies the delta stored in the CPU's class_data.
>
> Apart from the small reduction in line count, one advantage is that
> more validation of the models can be done unconditionally at startup,
> instead of happening dynamically if a CPU model is chosen.
>
> Based-on: <20250218165757.554178-1-pbonzini@redhat.com>
>
> Paolo
>
> v1->v2:
> - merged "remove target/riscv: remove unused macro DEFINE_CPU"
> - max SATP mode refactoring moved to its own series
> - included a couple of Philippe's patches from his "const class_data"
> series
> - RISCVCPUDef initializers all declared as const
>
> Paolo Bonzini (20):
> target/riscv: introduce RISCVCPUDef
> target/riscv: store RISCVCPUDef struct directly in the class
> target/riscv: merge riscv_cpu_class_init with the class_base function
> target/riscv: move RISCVCPUConfig fields to a header file
> target/riscv: add more RISCVCPUDef fields
> target/riscv: convert abstract CPU classes to RISCVCPUDef
> target/riscv: do not make RISCVCPUConfig fields conditional
> target/riscv: convert profile CPU models to RISCVCPUDef
> target/riscv: convert bare CPU models to RISCVCPUDef
> target/riscv: convert dynamic CPU models to RISCVCPUDef
> target/riscv: convert SiFive E CPU models to RISCVCPUDef
> target/riscv: convert ibex CPU models to RISCVCPUDef
> target/riscv: convert SiFive U models to RISCVCPUDef
> target/riscv: th: make CSR insertion test a bit more intuitive
> target/riscv: generalize custom CSR functionality
> target/riscv: convert TT C906 to RISCVCPUDef
> target/riscv: convert TT Ascalon to RISCVCPUDef
> target/riscv: convert Ventana V1 to RISCVCPUDef
> target/riscv: convert Xiangshan Nanhu to RISCVCPUDef
> target/riscv: remove .instance_post_init
>
> Philippe Mathieu-Daudé (2):
> target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL
> target/riscv: Convert misa_mxl_max using GLib macros
>
> target/riscv/cpu-qom.h | 2 +
> target/riscv/cpu.h | 27 +-
> target/riscv/cpu_cfg.h | 160 +-----
> target/riscv/cpu_cfg_fields.h.inc | 165 ++++++
> hw/riscv/boot.c | 2 +-
> target/riscv/cpu.c | 909 ++++++++++++++----------------
> target/riscv/csr.c | 2 +-
> target/riscv/gdbstub.c | 6 +-
> target/riscv/kvm/kvm-cpu.c | 23 +-
> target/riscv/machine.c | 6 +-
> target/riscv/tcg/tcg-cpu.c | 10 +-
> target/riscv/th_csr.c | 30 +-
> target/riscv/translate.c | 2 +-
> 13 files changed, 632 insertions(+), 712 deletions(-)
> create mode 100644 target/riscv/cpu_cfg_fields.h.inc
>
> --
> 2.48.1
>
[-- Attachment #2: Type: text/html, Size: 4931 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 00/22] target/riscv: declarative CPU definitions
2025-04-17 13:40 ` [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
@ 2025-04-24 10:37 ` Alistair Francis
0 siblings, 0 replies; 31+ messages in thread
From: Alistair Francis @ 2025-04-24 10:37 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel, Alistair Francis
On Thu, Apr 17, 2025 at 11:42 PM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> Hi Alistair,
>
> sorry for the stupid question—I am not sure whether you are going to give reviewed-by to the remaining patches, and also whether you would like me to submit the PR for this or not.
Sorry, just getting through a backlog. I have reviewed and applied the patches
Alistair
>
> Thanks in advance
>
> Paolo
>
> Il ven 28 feb 2025, 11:27 Paolo Bonzini <pbonzini@redhat.com> ha scritto:
>>
>> As in v1, what I really wanted to achieve was removing RISC-V's
>> use of .instance_post_init; that's because RISC-V operate with an
>> opposite conception of .instance_post_init compared to everyone
>> else: RISC-V wants to register properties there, whereas x86 and
>> hw/pci-bridge/pcie_root_port.c want to set them. While it's possible
>> to move RISC-V's code to instance_init, the others have to run after
>> global properties have been set by device_post_init().
>>
>> The way to get there is to make CPU definitions entirely declarative.
>> Previously, multiple instance_init functions each override the properties
>> that were set by the superclass, and the code used a mix of subclassing
>> and direct invocation of other functions. Now, instead, after .class_init
>> all the settings for each model are available in a RISCVCPUDef struct,
>> and the result is copied into the RISCVCPU at .instance_init time.
>> This is done with a single function that starts from the parent's
>> RISCVCPUDef and applies the delta stored in the CPU's class_data.
>>
>> Apart from the small reduction in line count, one advantage is that
>> more validation of the models can be done unconditionally at startup,
>> instead of happening dynamically if a CPU model is chosen.
>>
>> Based-on: <20250218165757.554178-1-pbonzini@redhat.com>
>>
>> Paolo
>>
>> v1->v2:
>> - merged "remove target/riscv: remove unused macro DEFINE_CPU"
>> - max SATP mode refactoring moved to its own series
>> - included a couple of Philippe's patches from his "const class_data" series
>> - RISCVCPUDef initializers all declared as const
>>
>> Paolo Bonzini (20):
>> target/riscv: introduce RISCVCPUDef
>> target/riscv: store RISCVCPUDef struct directly in the class
>> target/riscv: merge riscv_cpu_class_init with the class_base function
>> target/riscv: move RISCVCPUConfig fields to a header file
>> target/riscv: add more RISCVCPUDef fields
>> target/riscv: convert abstract CPU classes to RISCVCPUDef
>> target/riscv: do not make RISCVCPUConfig fields conditional
>> target/riscv: convert profile CPU models to RISCVCPUDef
>> target/riscv: convert bare CPU models to RISCVCPUDef
>> target/riscv: convert dynamic CPU models to RISCVCPUDef
>> target/riscv: convert SiFive E CPU models to RISCVCPUDef
>> target/riscv: convert ibex CPU models to RISCVCPUDef
>> target/riscv: convert SiFive U models to RISCVCPUDef
>> target/riscv: th: make CSR insertion test a bit more intuitive
>> target/riscv: generalize custom CSR functionality
>> target/riscv: convert TT C906 to RISCVCPUDef
>> target/riscv: convert TT Ascalon to RISCVCPUDef
>> target/riscv: convert Ventana V1 to RISCVCPUDef
>> target/riscv: convert Xiangshan Nanhu to RISCVCPUDef
>> target/riscv: remove .instance_post_init
>>
>> Philippe Mathieu-Daudé (2):
>> target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL
>> target/riscv: Convert misa_mxl_max using GLib macros
>>
>> target/riscv/cpu-qom.h | 2 +
>> target/riscv/cpu.h | 27 +-
>> target/riscv/cpu_cfg.h | 160 +-----
>> target/riscv/cpu_cfg_fields.h.inc | 165 ++++++
>> hw/riscv/boot.c | 2 +-
>> target/riscv/cpu.c | 909 ++++++++++++++----------------
>> target/riscv/csr.c | 2 +-
>> target/riscv/gdbstub.c | 6 +-
>> target/riscv/kvm/kvm-cpu.c | 23 +-
>> target/riscv/machine.c | 6 +-
>> target/riscv/tcg/tcg-cpu.c | 10 +-
>> target/riscv/th_csr.c | 30 +-
>> target/riscv/translate.c | 2 +-
>> 13 files changed, 632 insertions(+), 712 deletions(-)
>> create mode 100644 target/riscv/cpu_cfg_fields.h.inc
>>
>> --
>> 2.48.1
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2025-04-24 10:38 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
2025-02-28 10:27 ` [PATCH 01/22] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Paolo Bonzini
2025-03-06 0:46 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 02/22] target/riscv: Convert misa_mxl_max using GLib macros Paolo Bonzini
2025-03-06 0:47 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 03/22] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-02-28 17:19 ` Richard Henderson
2025-02-28 10:27 ` [PATCH 04/22] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-03-06 0:50 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 05/22] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-03-06 0:52 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 06/22] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-03-06 0:53 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 07/22] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-02-28 10:27 ` [PATCH 08/22] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-02-28 10:27 ` [PATCH 09/22] target/riscv: do not make RISCVCPUConfig fields conditional Paolo Bonzini
2025-02-28 10:27 ` [PATCH 10/22] target/riscv: convert profile CPU models to RISCVCPUDef Paolo Bonzini
2025-02-28 10:27 ` [PATCH 11/22] target/riscv: convert bare " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 12/22] target/riscv: convert dynamic " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 13/22] target/riscv: convert SiFive E " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 14/22] target/riscv: convert ibex " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 15/22] target/riscv: convert SiFive U " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 16/22] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-02-28 10:27 ` [PATCH 17/22] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-02-28 10:27 ` [PATCH 18/22] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-02-28 10:27 ` [PATCH 19/22] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 20/22] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 21/22] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 22/22] target/riscv: remove .instance_post_init Paolo Bonzini
2025-04-17 13:40 ` [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
2025-04-24 10:37 ` Alistair Francis
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