From: Alistair Francis <alistair23@gmail.com>
To: Jim Shu <jim.shu@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Frank Chang <frank.chang@sifive.com>,
Bin Meng <bin.meng@windriver.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [PATCH v2 0/2] Align SiFive PDMA behavior to real hardware
Date: Wed, 5 Jan 2022 07:54:29 +1000 [thread overview]
Message-ID: <CAKmqyKMftmh67=nM4Jcre1LOvv9Tf33UuhcOVC-jbdpGkC1XOw@mail.gmail.com> (raw)
In-Reply-To: <20220104063408.658169-1-jim.shu@sifive.com>
On Tue, Jan 4, 2022 at 4:56 PM Jim Shu <jim.shu@sifive.com> wrote:
>
> HiFive Unmatched PDMA supports high/low 32-bit access of 64-bit
> register, but QEMU emulation supports low part access now. Enhance QEMU
> emulation to support high 32-bit access.
>
> Also, permit 4/8-byte valid access in PDMA as we have verified 32/64-bit
> accesses of PDMA registers are supported.
>
> Changelog:
>
> v2:
> * Fix high 32-bit write access of 64-bit RO registers
> * Fix commit log
>
> Jim Shu (2):
> hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
> hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> hw/dma/sifive_pdma.c | 181 +++++++++++++++++++++++++++++++++++++------
> 1 file changed, 159 insertions(+), 22 deletions(-)
>
> --
> 2.25.1
>
>
prev parent reply other threads:[~2022-01-04 21:56 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-04 6:34 [PATCH v2 0/2] Align SiFive PDMA behavior to real hardware Jim Shu
2022-01-04 6:34 ` [PATCH v2 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register Jim Shu
2022-01-04 6:34 ` [PATCH v2 2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers Jim Shu
2022-01-04 21:54 ` Alistair Francis [this message]
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