From: Alistair Francis <alistair23@gmail.com>
To: Atish Patra <atishp@rivosinc.com>
Cc: Kaiwen Xue <kaiwenx@rivosinc.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Weiwei Li <liwei1518@gmail.com>,
kaiwenxue1@gmail.com
Subject: Re: [PATCH v4 2/5] target/riscv: Add cycle & instret privilege mode filtering properties
Date: Mon, 22 Jan 2024 14:55:27 +1000 [thread overview]
Message-ID: <CAKmqyKMgy8UGJ1soavRFh0rWJu2iyY-WbevSh+Ot=zuPVUz6Hw@mail.gmail.com> (raw)
In-Reply-To: <20240109002554.646572-3-atishp@rivosinc.com>
On Tue, Jan 9, 2024 at 11:04 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> From: Kaiwen Xue <kaiwenx@rivosinc.com>
>
> This adds the properties for ISA extension smcntrpmf. Patches
> implementing it will follow.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu_cfg.h | 1 +
> 2 files changed, 3 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 83c7c0cf07be..501ae560ec29 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -144,6 +144,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
> ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
> ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
> + ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
> ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
> ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
> ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
> @@ -1296,6 +1297,7 @@ const char *riscv_get_misa_ext_description(uint32_t bit)
> const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> /* Defaults for standard extensions */
> MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
> + MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false),
> MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
> MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true),
> MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index f4605fb190b9..00c34fdd3209 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -72,6 +72,7 @@ struct RISCVCPUConfig {
> bool ext_zihpm;
> bool ext_smstateen;
> bool ext_sstc;
> + bool ext_smcntrpmf;
> bool ext_svadu;
> bool ext_svinval;
> bool ext_svnapot;
> --
> 2.34.1
>
>
next prev parent reply other threads:[~2024-01-22 4:56 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-09 0:25 [PATCH v4 0/5] Add ISA extension smcntrpmf support Atish Patra
2024-01-09 0:25 ` [PATCH v4 1/5] target/riscv: Fix the predicate functions for mhpmeventhX CSRs Atish Patra
2024-01-09 0:25 ` [PATCH v4 2/5] target/riscv: Add cycle & instret privilege mode filtering properties Atish Patra
2024-01-09 18:37 ` Daniel Henrique Barboza
2024-01-22 4:55 ` Alistair Francis [this message]
2024-01-09 0:25 ` [PATCH v4 3/5] target/riscv: Add cycle & instret privilege mode filtering definitions Atish Patra
2024-01-22 4:56 ` Alistair Francis
2024-01-09 0:25 ` [PATCH v4 4/5] target/riscv: Add cycle & instret privilege mode filtering support Atish Patra
2024-01-22 4:58 ` Alistair Francis
2024-01-09 0:25 ` [PATCH v4 5/5] target/riscv: Implement privilege mode filtering for cycle/instret Atish Patra
2024-01-22 5:04 ` Alistair Francis
2024-01-24 0:15 ` Atish Kumar Patra
2024-02-05 19:38 ` Atish Kumar Patra
2024-02-15 4:45 ` Alistair Francis
2024-02-15 4:45 ` Alistair Francis
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