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That's all we know. X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Richard Henderson , "qemu-devel@nongnu.org Developers" , wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, May 21, 2020 at 4:21 AM LIU Zhiwei wrote: > > Signed-off-by: LIU Zhiwei > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 10 +++++++ > target/riscv/insn32.decode | 4 +++ > target/riscv/insn_trans/trans_rvv.inc.c | 5 ++++ > target/riscv/vector_helper.c | 39 +++++++++++++++++++++++++ > 4 files changed, 58 insertions(+) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index ce31577ea9..17fd02c323 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -1073,3 +1073,13 @@ DEF_HELPER_6(vwredsumu_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vwredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > + > +DEF_HELPER_6(vfredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredsum_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredmax_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredmax_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredmin_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredmin_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index b69d804fda..0592075167 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -539,6 +539,10 @@ vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm > vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm > vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm > vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm > +# Vector ordered and unordered reduction sum > +vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm > +vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm > +vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm > > vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm > vsetvl 1000000 ..... ..... 111 ..... 1010111 @r > diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c > index 8d75b3ca84..d74054ff04 100644 > --- a/target/riscv/insn_trans/trans_rvv.inc.c > +++ b/target/riscv/insn_trans/trans_rvv.inc.c > @@ -2337,3 +2337,8 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check) > /* Vector Widening Integer Reduction Instructions */ > GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check) > GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check) > + > +/* Vector Single-Width Floating-Point Reduction Instructions */ > +GEN_OPFVV_TRANS(vfredsum_vs, reduction_check) > +GEN_OPFVV_TRANS(vfredmax_vs, reduction_check) > +GEN_OPFVV_TRANS(vfredmin_vs, reduction_check) > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 5035e0bb0e..f37b65288a 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -4416,3 +4416,42 @@ GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD, clearq) > GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD, clearh) > GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD, clearl) > GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD, clearq) > + > +/* Vector Single-Width Floating-Point Reduction Instructions */ > +#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\ > +void HELPER(NAME)(void *vd, void *v0, void *vs1, \ > + void *vs2, CPURISCVState *env, \ > + uint32_t desc) \ > +{ \ > + uint32_t mlen = vext_mlen(desc); \ > + uint32_t vm = vext_vm(desc); \ > + uint32_t vl = env->vl; \ > + uint32_t i; \ > + uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \ > + TD s1 = *((TD *)vs1 + HD(0)); \ > + \ > + for (i = 0; i < vl; i++) { \ > + TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ > + if (!vm && !vext_elem_mask(v0, mlen, i)) { \ > + continue; \ > + } \ > + s1 = OP(s1, (TD)s2, &env->fp_status); \ > + } \ > + *((TD *)vd + HD(0)) = s1; \ > + CLEAR_FN(vd, 1, sizeof(TD), tot); \ > +} > + > +/* Unordered sum */ > +GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add, clearh) > +GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add, clearl) > +GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add, clearq) > + > +/* Maximum value */ > +GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum, clearh) > +GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum, clearl) > +GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum, clearq) > + > +/* Minimum value */ > +GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum, clearh) > +GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum, clearl) > +GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum, clearq) > -- > 2.23.0 > >