[PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions

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* [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions
@ 2022-01-18  1:45 frank.chang
  2022-01-18  1:45 ` [PATCH v2 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V frank.chang
                   ` (17 more replies)
  0 siblings, 18 replies; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel; +Cc: Frank Chang, qemu-riscv

From: Frank Chang <frank.chang@sifive.com>

In RVV v1.0 spec, several Zve* vector extensions for embedded processors
are defined in Chapter 18.2:
https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#zve-vector-extensions-for-embedded-processors

This patchset implements Zve32f and Zve64f extensions.

The port is available at:
https://github.com/sifive/qemu/tree/rvv-zve32f-zve64f-upstream-v2

Zve32f can be enabled with -cpu option: Zve32f=true and
Zve64f can be enabled with -cpu option: Zve64f=true.
V is not required to be enabled explicitly.

Here's the inclusion diagram for the six standard vector extensions
quoted from Nick Knight <nick.knight@sifive.com>:

      V
      |
    Zve64d
      |
    Zve64f
   /      \
Zve64x   Zve32f
   \      /
    Zve32x

Changelog:

v2:
  * Replace hardcoded TARGET_RISCV32 macro with get_xl().

Frank Chang (17):
  target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
  target/riscv: rvv-1.0: Add Zve64f support for configuration insns
  target/riscv: rvv-1.0: Add Zve64f support for load and store insns
  target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
  target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx
    insns
  target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
  target/riscv: rvv-1.0: Add Zve64f support for single-width fp
    reduction insns
  target/riscv: rvv-1.0: Add Zve64f support for widening type-convert
    insns
  target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert
    insns
  target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
  target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
  target/riscv: rvv-1.0: Add Zve32f support for configuration insns
  target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
  target/riscv: rvv-1.0: Add Zve32f support for single-width fp
    reduction insns
  target/riscv: rvv-1.0: Add Zve32f support for widening type-convert
    insns
  target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert
    insns
  target/riscv: rvv-1.0: Allow Zve32f extension to be turned on

 target/riscv/cpu.c                      |   6 +
 target/riscv/cpu.h                      |   2 +
 target/riscv/cpu_helper.c               |   5 +-
 target/riscv/csr.c                      |   6 +-
 target/riscv/insn_trans/trans_rvv.c.inc | 219 ++++++++++++++++++++----
 target/riscv/translate.c                |   4 +
 6 files changed, 205 insertions(+), 37 deletions(-)

--
2.31.1



^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v2 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
@ 2022-01-18  1:45 ` frank.chang
  2022-01-18  1:45 ` [PATCH v2 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns frank.chang
                   ` (16 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: Frank Chang, Alistair Francis, Bin Meng, qemu-riscv,
	Palmer Dabbelt

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c        | 4 ++++
 target/riscv/cpu.h        | 1 +
 target/riscv/cpu_helper.c | 5 ++++-
 target/riscv/csr.c        | 6 +++++-
 target/riscv/translate.c  | 2 ++
 5 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9bc25d3055..2ba22503da 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -589,6 +589,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             }
             set_vext_version(env, vext_version);
         }
+        if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) {
+            error_setg(errp, "Zve64f extension depends upon RVF.");
+            return;
+        }
         if (cpu->cfg.ext_j) {
             ext |= RVJ;
         }
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4d63086765..86cc94d3bb 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -329,6 +329,7 @@ struct RISCVCPU {
         bool ext_icsr;
         bool ext_zfh;
         bool ext_zfhmin;
+        bool ext_zve64f;
 
         char *priv_spec;
         char *user_spec;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 434a83e66a..43d498aae1 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -69,12 +69,15 @@ static RISCVMXL cpu_get_xl(CPURISCVState *env)
 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                           target_ulong *cs_base, uint32_t *pflags)
 {
+    CPUState *cs = env_cpu(env);
+    RISCVCPU *cpu = RISCV_CPU(cs);
+
     uint32_t flags = 0;
 
     *pc = env->pc;
     *cs_base = 0;
 
-    if (riscv_has_ext(env, RVV)) {
+    if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index adb3d4381d..e9311cfd9d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -47,7 +47,11 @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    if (env->misa_ext & RVV) {
+    CPUState *cs = env_cpu(env);
+    RISCVCPU *cpu = RISCV_CPU(cs);
+
+    if (env->misa_ext & RVV ||
+        cpu->cfg.ext_zve64f) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 615048ec87..d3c0d44e2e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -79,6 +79,7 @@ typedef struct DisasContext {
     bool ext_ifencei;
     bool ext_zfh;
     bool ext_zfhmin;
+    bool ext_zve64f;
     bool hlsx;
     /* vector extension */
     bool vill;
@@ -894,6 +895,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
     ctx->ext_zfh = cpu->cfg.ext_zfh;
     ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
+    ctx->ext_zve64f = cpu->cfg.ext_zve64f;
     ctx->vlen = cpu->cfg.vlen;
     ctx->elen = cpu->cfg.elen;
     ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
-- 
2.31.1



^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
  2022-01-18  1:45 ` [PATCH v2 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V frank.chang
@ 2022-01-18  1:45 ` frank.chang
  2022-01-18  1:45 ` [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns frank.chang
                   ` (15 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, Frank Chang, Bin Meng, Richard Henderson,
	Alistair Francis, Palmer Dabbelt, LIU Zhiwei

From: Frank Chang <frank.chang@sifive.com>

All Zve* extensions support the vector configuration instructions.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 6c285c958b..5b47729a21 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -129,7 +129,8 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
 {
     TCGv s1, dst;
 
-    if (!require_rvv(s) || !has_ext(s, RVV)) {
+    if (!require_rvv(s) ||
+        !(has_ext(s, RVV) || s->ext_zve64f)) {
         return false;
     }
 
@@ -164,7 +165,8 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
 {
     TCGv dst;
 
-    if (!require_rvv(s) || !has_ext(s, RVV)) {
+    if (!require_rvv(s) ||
+        !(has_ext(s, RVV) || s->ext_zve64f)) {
         return false;
     }
 
-- 
2.31.1



^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
  2022-01-18  1:45 ` [PATCH v2 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V frank.chang
  2022-01-18  1:45 ` [PATCH v2 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns frank.chang
@ 2022-01-18  1:45 ` frank.chang
  2022-01-18  4:42   ` Alistair Francis
  2022-01-18  1:45 ` [PATCH v2 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns frank.chang
                   ` (14 subsequent siblings)
  17 siblings, 1 reply; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, Frank Chang, Bin Meng, Richard Henderson,
	Palmer Dabbelt, Alistair Francis, LIU Zhiwei

From: Frank Chang <frank.chang@sifive.com>

All Zve* extensions support all vector load and store instructions,
except Zve64* extensions do not support EEW=64 for index values when
XLEN=32.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 5b47729a21..0bf41aaa1e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -263,10 +263,21 @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
                                 uint8_t eew)
 {
     int8_t emul = eew - s->sew + s->lmul;
-    return (emul >= -3 && emul <= 3) &&
-            require_align(vs2, emul) &&
-            require_align(vd, s->lmul) &&
-            require_nf(vd, nf, s->lmul);
+    bool ret = (emul >= -3 && emul <= 3) &&
+               require_align(vs2, emul) &&
+               require_align(vd, s->lmul) &&
+               require_nf(vd, nf, s->lmul);
+
+    /*
+     * All Zve* extensions support all vector load and store instructions,
+     * except Zve64* extensions do not support EEW=64 for index values
+     * when XLEN=32. (Section 18.2)
+     */
+    if (get_xl(s) == MXL_RV32) {
+        ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
+    }
+
+    return ret;
 }
 
 /*
-- 
2.31.1



^ permalink raw reply related	[flat|nested] 20+ messages in thread

* Re: [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns
  2022-01-18  1:45 ` [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns frank.chang
@ 2022-01-18  4:42   ` Alistair Francis
  0 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2022-01-18  4:42 UTC (permalink / raw)
  To: Frank Chang
  Cc: open list:RISC-V, Bin Meng, Richard Henderson,
	qemu-devel@nongnu.org Developers, Palmer Dabbelt,
	Alistair Francis, LIU Zhiwei

On Tue, Jan 18, 2022 at 11:59 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> All Zve* extensions support all vector load and store instructions,
> except Zve64* extensions do not support EEW=64 for index values when
> XLEN=32.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 19 +++++++++++++++----
>  1 file changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 5b47729a21..0bf41aaa1e 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -263,10 +263,21 @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
>                                  uint8_t eew)
>  {
>      int8_t emul = eew - s->sew + s->lmul;
> -    return (emul >= -3 && emul <= 3) &&
> -            require_align(vs2, emul) &&
> -            require_align(vd, s->lmul) &&
> -            require_nf(vd, nf, s->lmul);
> +    bool ret = (emul >= -3 && emul <= 3) &&
> +               require_align(vs2, emul) &&
> +               require_align(vd, s->lmul) &&
> +               require_nf(vd, nf, s->lmul);
> +
> +    /*
> +     * All Zve* extensions support all vector load and store instructions,
> +     * except Zve64* extensions do not support EEW=64 for index values
> +     * when XLEN=32. (Section 18.2)
> +     */
> +    if (get_xl(s) == MXL_RV32) {
> +        ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
> +    }
> +
> +    return ret;
>  }
>
>  /*
> --
> 2.31.1
>
>


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v2 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
                   ` (2 preceding siblings ...)
  2022-01-18  1:45 ` [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns frank.chang
@ 2022-01-18  1:45 ` frank.chang
  2022-01-18  1:45 ` [PATCH v2 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns frank.chang
                   ` (13 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, Frank Chang, Bin Meng, Richard Henderson,
	Alistair Francis, Palmer Dabbelt, LIU Zhiwei

From: Frank Chang <frank.chang@sifive.com>

All Zve* extensions support all vector integer instructions,
except that the vmulh integer multiply variants that return the
high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx,
vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++++++++++++++++++----
 1 file changed, 33 insertions(+), 6 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 0bf41aaa1e..e64dddda28 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1908,14 +1908,41 @@ GEN_OPIVX_TRANS(vmaxu_vx, opivx_check)
 GEN_OPIVX_TRANS(vmax_vx,  opivx_check)
 
 /* Vector Single-Width Integer Multiply Instructions */
+
+static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a)
+{
+    /*
+     * All Zve* extensions support all vector integer instructions,
+     * except that the vmulh integer multiply variants
+     * that return the high word of the product
+     * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx)
+     * are not included for EEW=64 in Zve64*. (Section 18.2)
+     */
+    return opivv_check(s, a) &&
+           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+}
+
+static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
+{
+    /*
+     * All Zve* extensions support all vector integer instructions,
+     * except that the vmulh integer multiply variants
+     * that return the high word of the product
+     * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx)
+     * are not included for EEW=64 in Zve64*. (Section 18.2)
+     */
+    return opivx_check(s, a) &&
+           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+}
+
 GEN_OPIVV_GVEC_TRANS(vmul_vv,  mul)
-GEN_OPIVV_TRANS(vmulh_vv, opivv_check)
-GEN_OPIVV_TRANS(vmulhu_vv, opivv_check)
-GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check)
+GEN_OPIVV_TRANS(vmulh_vv, vmulh_vv_check)
+GEN_OPIVV_TRANS(vmulhu_vv, vmulh_vv_check)
+GEN_OPIVV_TRANS(vmulhsu_vv, vmulh_vv_check)
 GEN_OPIVX_GVEC_TRANS(vmul_vx,  muls)
-GEN_OPIVX_TRANS(vmulh_vx, opivx_check)
-GEN_OPIVX_TRANS(vmulhu_vx, opivx_check)
-GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check)
+GEN_OPIVX_TRANS(vmulh_vx, vmulh_vx_check)
+GEN_OPIVX_TRANS(vmulhu_vx, vmulh_vx_check)
+GEN_OPIVX_TRANS(vmulhsu_vx, vmulh_vx_check)
 
 /* Vector Integer Divide Instructions */
 GEN_OPIVV_TRANS(vdivu_vv, opivv_check)
-- 
2.31.1



^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
                   ` (3 preceding siblings ...)
  2022-01-18  1:45 ` [PATCH v2 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns frank.chang
@ 2022-01-18  1:45 ` frank.chang
  2022-01-18  1:45 ` [PATCH v2 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns frank.chang
                   ` (12 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, Frank Chang, Bin Meng, Richard Henderson,
	Alistair Francis, Palmer Dabbelt, LIU Zhiwei

From: Frank Chang <frank.chang@sifive.com>

All Zve* extensions support all vector fixed-point arithmetic
instructions, except that vsmul.vv and vsmul.vx are not supported
for EEW=64 in Zve64*.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 27 +++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index e64dddda28..8e493b7933 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2123,8 +2123,31 @@ GEN_OPIVX_TRANS(vasub_vx,  opivx_check)
 GEN_OPIVX_TRANS(vasubu_vx,  opivx_check)
 
 /* Vector Single-Width Fractional Multiply with Rounding and Saturation */
-GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
-GEN_OPIVX_TRANS(vsmul_vx,  opivx_check)
+
+static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
+{
+    /*
+     * All Zve* extensions support all vector fixed-point arithmetic
+     * instructions, except that vsmul.vv and vsmul.vx are not supported
+     * for EEW=64 in Zve64*. (Section 18.2)
+     */
+    return opivv_check(s, a) &&
+           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+}
+
+static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
+{
+    /*
+     * All Zve* extensions support all vector fixed-point arithmetic
+     * instructions, except that vsmul.vv and vsmul.vx are not supported
+     * for EEW=64 in Zve64*. (Section 18.2)
+     */
+    return opivx_check(s, a) &&
+           (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+}
+
+GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)
+GEN_OPIVX_TRANS(vsmul_vx,  vsmul_vx_check)
 
 /* Vector Single-Width Scaling Shift Instructions */
 GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
-- 
2.31.1



^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
                   ` (4 preceding siblings ...)
  2022-01-18  1:45 ` [PATCH v2 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns frank.chang
@ 2022-01-18  1:45 ` frank.chang
  2022-01-18  1:45 ` [PATCH v2 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns frank.chang
                   ` (11 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, Frank Chang, Bin Meng, Richard Henderson,
	Alistair Francis, Palmer Dabbelt, LIU Zhiwei

From: Frank Chang <frank.chang@sifive.com>

Zve64f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 41 +++++++++++++++++++------
 1 file changed, 31 insertions(+), 10 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 8e493b7933..56246a5d88 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -66,6 +66,17 @@ static bool require_scale_rvf(DisasContext *s)
     }
 }
 
+static bool require_zve64f(DisasContext *s)
+{
+    /* RVV + Zve64f = RVV. */
+    if (has_ext(s, RVV)) {
+        return true;
+    }
+
+    /* Zve64f doesn't support FP64. (Section 18.2) */
+    return s->ext_zve64f ? s->sew <= MO_32 : true;
+}
+
 /* Destination vector register group cannot overlap source mask register. */
 static bool require_vm(int vm, int vd)
 {
@@ -2206,7 +2217,8 @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
+           vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_zve64f(s);
 }
 
 /* OPFVV without GVEC IR */
@@ -2286,7 +2298,8 @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_ss(s, a->rd, a->rs2, a->vm);
+           vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+           require_zve64f(s);
 }
 
 /* OPFVF without GVEC IR */
@@ -2503,7 +2516,8 @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
            /* OPFV instructions ignore vs1 check */
-           vext_check_ss(s, a->rd, a->rs2, a->vm);
+           vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+           require_zve64f(s);
 }
 
 static bool do_opfv(DisasContext *s, arg_rmr *a,
@@ -2568,7 +2582,8 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_mss(s, a->rd, a->rs1, a->rs2);
+           vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
+           require_zve64f(s);
 }
 
 GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
@@ -2581,7 +2596,8 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_ms(s, a->rd, a->rs2);
+           vext_check_ms(s, a->rd, a->rs2) &&
+           require_zve64f(s);
 }
 
 GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
@@ -2602,7 +2618,8 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
     if (require_rvv(s) &&
         require_rvf(s) &&
         vext_check_isa_ill(s) &&
-        require_align(a->rd, s->lmul)) {
+        require_align(a->rd, s->lmul) &&
+        require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
         TCGv_i64 t1;
@@ -3328,7 +3345,8 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
 {
     if (require_rvv(s) &&
         require_rvf(s) &&
-        vext_check_isa_ill(s)) {
+        vext_check_isa_ill(s) &&
+        require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
         unsigned int ofs = (8 << s->sew);
@@ -3354,7 +3372,8 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
 {
     if (require_rvv(s) &&
         require_rvf(s) &&
-        vext_check_isa_ill(s)) {
+        vext_check_isa_ill(s) &&
+        require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
         /* The instructions ignore LMUL and vector register group. */
@@ -3405,13 +3424,15 @@ GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check)
 static bool fslideup_check(DisasContext *s, arg_rmrr *a)
 {
     return slideup_check(s, a) &&
-           require_rvf(s);
+           require_rvf(s) &&
+           require_zve64f(s);
 }
 
 static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
 {
     return slidedown_check(s, a) &&
-           require_rvf(s);
+           require_rvf(s) &&
+           require_zve64f(s);
 }
 
 GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check)
-- 
2.31.1



^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
                   ` (5 preceding siblings ...)
  2022-01-18  1:45 ` [PATCH v2 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns frank.chang
@ 2022-01-18  1:45 ` frank.chang
  2022-01-18  1:45 ` [PATCH v2 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns frank.chang
                   ` (10 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, Frank Chang, Bin Meng, Richard Henderson,
	Alistair Francis, Palmer Dabbelt, LIU Zhiwei

From: Frank Chang <frank.chang@sifive.com>

Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve64f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 56246a5d88..08f25e3ce4 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2937,7 +2937,8 @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
 static bool freduction_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_check(s, a) &&
-           require_rvf(s);
+           require_rvf(s) &&
+           require_zve64f(s);
 }
 
 GEN_OPFVV_TRANS(vfredsum_vs, freduction_check)
-- 
2.31.1



^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
                   ` (6 preceding siblings ...)
  2022-01-18  1:45 ` [PATCH v2 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns frank.chang
@ 2022-01-18  1:45 ` frank.chang
  2022-01-18  1:45 ` [PATCH v2 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing " frank.chang
                   ` (9 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, Frank Chang, Bin Meng, Richard Henderson,
	Alistair Francis, Palmer Dabbelt, LIU Zhiwei

From: Frank Chang <frank.chang@sifive.com>

Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 32 +++++++++++++++++++------
 1 file changed, 25 insertions(+), 7 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 08f25e3ce4..58f12366dd 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -77,6 +77,17 @@ static bool require_zve64f(DisasContext *s)
     return s->ext_zve64f ? s->sew <= MO_32 : true;
 }
 
+static bool require_scale_zve64f(DisasContext *s)
+{
+    /* RVV + Zve64f = RVV. */
+    if (has_ext(s, RVV)) {
+        return true;
+    }
+
+    /* Zve64f doesn't support FP64. (Section 18.2) */
+    return s->ext_zve64f ? s->sew <= MO_16 : true;
+}
+
 /* Destination vector register group cannot overlap source mask register. */
 static bool require_vm(int vm, int vd)
 {
@@ -2333,7 +2344,8 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
+           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 /* OPFVV with WIDEN */
@@ -2372,7 +2384,8 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_ds(s, a->rd, a->rs2, a->vm);
+           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 /* OPFVF with WIDEN */
@@ -2402,7 +2415,8 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
+           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 /* WIDEN OPFVV with WIDEN */
@@ -2441,7 +2455,8 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_dd(s, a->rd, a->rs2, a->vm);
+           vext_check_dd(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 /* WIDEN OPFVF with WIDEN */
@@ -2700,14 +2715,16 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
 static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
-           require_rvf(s);
+           require_rvf(s) &&
+           require_zve64f(s);
 }
 
 static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           (s->sew != MO_8) &&
+           require_scale_zve64f(s);
 }
 
 #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -2758,7 +2775,8 @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
            require_scale_rvf(s) &&
            vext_check_isa_ill(s) &&
            /* OPFV widening instructions ignore vs1 check */
-           vext_check_ds(s, a->rd, a->rs2, a->vm);
+           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 #define GEN_OPFXV_WIDEN_TRANS(NAME)                                \
-- 
2.31.1



^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
                   ` (7 preceding siblings ...)
  2022-01-18  1:45 ` [PATCH v2 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns frank.chang
@ 2022-01-18  1:45 ` frank.chang
  2022-01-18  1:45 ` [PATCH v2 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on frank.chang
                   ` (8 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, Frank Chang, Bin Meng, Richard Henderson,
	Alistair Francis, Palmer Dabbelt, LIU Zhiwei

From: Frank Chang <frank.chang@sifive.com>

Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 58f12366dd..9fa3862620 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2826,14 +2826,16 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvf(s) &&
-           (s->sew != MO_64);
+           (s->sew != MO_64) &&
+           require_zve64f(s);
 }
 
 static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           (s->sew != MO_8) &&
+           require_scale_zve64f(s);
 }
 
 #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -2882,7 +2884,8 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
            require_scale_rvf(s) &&
            vext_check_isa_ill(s) &&
            /* OPFV narrowing instructions ignore vs1 check */
-           vext_check_sd(s, a->rd, a->rs2, a->vm);
+           vext_check_sd(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve64f(s);
 }
 
 #define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM)                  \
-- 
2.31.1



^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
                   ` (8 preceding siblings ...)
  2022-01-18  1:45 ` [PATCH v2 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing " frank.chang
@ 2022-01-18  1:45 ` frank.chang
  2022-01-18  1:45 ` [PATCH v2 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V frank.chang
                   ` (7 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: Frank Chang, Alistair Francis, Bin Meng, qemu-riscv,
	Palmer Dabbelt

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2ba22503da..4bca1cd289 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -664,6 +664,7 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
     DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
     DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
+    DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
 
-- 
2.31.1



^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
                   ` (9 preceding siblings ...)
  2022-01-18  1:45 ` [PATCH v2 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on frank.chang
@ 2022-01-18  1:45 ` frank.chang
  2022-01-18  1:45 ` [PATCH v2 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns frank.chang
                   ` (6 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: Frank Chang, Alistair Francis, Bin Meng, qemu-riscv,
	Palmer Dabbelt

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c        | 4 ++--
 target/riscv/cpu.h        | 1 +
 target/riscv/cpu_helper.c | 2 +-
 target/riscv/csr.c        | 2 +-
 target/riscv/translate.c  | 2 ++
 5 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4bca1cd289..0898954c02 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -589,8 +589,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             }
             set_vext_version(env, vext_version);
         }
-        if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) {
-            error_setg(errp, "Zve64f extension depends upon RVF.");
+        if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
+            error_setg(errp, "Zve32f/Zve64f extension depends upon RVF.");
             return;
         }
         if (cpu->cfg.ext_j) {
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 86cc94d3bb..21772496b3 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -329,6 +329,7 @@ struct RISCVCPU {
         bool ext_icsr;
         bool ext_zfh;
         bool ext_zfhmin;
+        bool ext_zve32f;
         bool ext_zve64f;
 
         char *priv_spec;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 43d498aae1..afee770951 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -77,7 +77,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
     *pc = env->pc;
     *cs_base = 0;
 
-    if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) {
+    if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e9311cfd9d..a9e7ac903b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -51,7 +51,7 @@ static RISCVException vs(CPURISCVState *env, int csrno)
     RISCVCPU *cpu = RISCV_CPU(cs);
 
     if (env->misa_ext & RVV ||
-        cpu->cfg.ext_zve64f) {
+        cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d3c0d44e2e..330904265e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -79,6 +79,7 @@ typedef struct DisasContext {
     bool ext_ifencei;
     bool ext_zfh;
     bool ext_zfhmin;
+    bool ext_zve32f;
     bool ext_zve64f;
     bool hlsx;
     /* vector extension */
@@ -895,6 +896,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
     ctx->ext_zfh = cpu->cfg.ext_zfh;
     ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
+    ctx->ext_zve32f = cpu->cfg.ext_zve32f;
     ctx->ext_zve64f = cpu->cfg.ext_zve64f;
     ctx->vlen = cpu->cfg.vlen;
     ctx->elen = cpu->cfg.elen;
-- 
2.31.1



^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
                   ` (10 preceding siblings ...)
  2022-01-18  1:45 ` [PATCH v2 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V frank.chang
@ 2022-01-18  1:45 ` frank.chang
  2022-01-18  1:45 ` [PATCH v2 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns frank.chang
                   ` (5 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, Frank Chang, Bin Meng, Richard Henderson,
	Alistair Francis, Palmer Dabbelt, LIU Zhiwei

From: Frank Chang <frank.chang@sifive.com>

All Zve* extensions support the vector configuration instructions.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 9fa3862620..fd6e74c232 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -152,7 +152,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
     TCGv s1, dst;
 
     if (!require_rvv(s) ||
-        !(has_ext(s, RVV) || s->ext_zve64f)) {
+        !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
         return false;
     }
 
@@ -188,7 +188,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
     TCGv dst;
 
     if (!require_rvv(s) ||
-        !(has_ext(s, RVV) || s->ext_zve64f)) {
+        !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
         return false;
     }
 
-- 
2.31.1



^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
                   ` (11 preceding siblings ...)
  2022-01-18  1:45 ` [PATCH v2 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns frank.chang
@ 2022-01-18  1:45 ` frank.chang
  2022-01-18  1:45 ` [PATCH v2 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns frank.chang
                   ` (4 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, Frank Chang, Bin Meng, Richard Henderson,
	Alistair Francis, Palmer Dabbelt, LIU Zhiwei

From: Frank Chang <frank.chang@sifive.com>

Zve32f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index fd6e74c232..fe4ad5d008 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -66,6 +66,17 @@ static bool require_scale_rvf(DisasContext *s)
     }
 }
 
+static bool require_zve32f(DisasContext *s)
+{
+    /* RVV + Zve32f = RVV. */
+    if (has_ext(s, RVV)) {
+        return true;
+    }
+
+    /* Zve32f doesn't support FP64. (Section 18.2) */
+    return s->ext_zve32f ? s->sew <= MO_32 : true;
+}
+
 static bool require_zve64f(DisasContext *s)
 {
     /* RVV + Zve64f = RVV. */
@@ -2229,6 +2240,7 @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
            vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -2310,6 +2322,7 @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
            vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -2532,6 +2545,7 @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
            vext_check_isa_ill(s) &&
            /* OPFV instructions ignore vs1 check */
            vext_check_ss(s, a->rd, a->rs2, a->vm) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -2598,6 +2612,7 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
            vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -2612,6 +2627,7 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
            vext_check_ms(s, a->rd, a->rs2) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -2634,6 +2650,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
         require_rvf(s) &&
         vext_check_isa_ill(s) &&
         require_align(a->rd, s->lmul) &&
+        require_zve32f(s) &&
         require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
@@ -3368,6 +3385,7 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
     if (require_rvv(s) &&
         require_rvf(s) &&
         vext_check_isa_ill(s) &&
+        require_zve32f(s) &&
         require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
@@ -3395,6 +3413,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
     if (require_rvv(s) &&
         require_rvf(s) &&
         vext_check_isa_ill(s) &&
+        require_zve32f(s) &&
         require_zve64f(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
@@ -3447,6 +3466,7 @@ static bool fslideup_check(DisasContext *s, arg_rmrr *a)
 {
     return slideup_check(s, a) &&
            require_rvf(s) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -3454,6 +3474,7 @@ static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
 {
     return slidedown_check(s, a) &&
            require_rvf(s) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
-- 
2.31.1



^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
                   ` (12 preceding siblings ...)
  2022-01-18  1:45 ` [PATCH v2 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns frank.chang
@ 2022-01-18  1:45 ` frank.chang
  2022-01-18  1:45 ` [PATCH v2 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns frank.chang
                   ` (3 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, Frank Chang, Bin Meng, Richard Henderson,
	Alistair Francis, Palmer Dabbelt, LIU Zhiwei

From: Frank Chang <frank.chang@sifive.com>

Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve32f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index fe4ad5d008..b02bb555a6 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2976,6 +2976,7 @@ static bool freduction_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_check(s, a) &&
            require_rvf(s) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
-- 
2.31.1



^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
                   ` (13 preceding siblings ...)
  2022-01-18  1:45 ` [PATCH v2 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns frank.chang
@ 2022-01-18  1:45 ` frank.chang
  2022-01-18  1:45 ` [PATCH v2 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing " frank.chang
                   ` (2 subsequent siblings)
  17 siblings, 0 replies; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, Frank Chang, Bin Meng, Richard Henderson,
	Alistair Francis, Palmer Dabbelt, LIU Zhiwei

From: Frank Chang <frank.chang@sifive.com>

Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index b02bb555a6..f2d3c9e8b9 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -77,6 +77,17 @@ static bool require_zve32f(DisasContext *s)
     return s->ext_zve32f ? s->sew <= MO_32 : true;
 }
 
+static bool require_scale_zve32f(DisasContext *s)
+{
+    /* RVV + Zve32f = RVV. */
+    if (has_ext(s, RVV)) {
+        return true;
+    }
+
+    /* Zve32f doesn't support FP64. (Section 18.2) */
+    return s->ext_zve64f ? s->sew <= MO_16 : true;
+}
+
 static bool require_zve64f(DisasContext *s)
 {
     /* RVV + Zve64f = RVV. */
@@ -2358,6 +2369,7 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_scale_zve32f(s) &&
            require_scale_zve64f(s);
 }
 
@@ -2398,6 +2410,7 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve32f(s) &&
            require_scale_zve64f(s);
 }
 
@@ -2429,6 +2442,7 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_scale_zve32f(s) &&
            require_scale_zve64f(s);
 }
 
@@ -2469,6 +2483,7 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dd(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve32f(s) &&
            require_scale_zve64f(s);
 }
 
@@ -2733,6 +2748,7 @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
            require_rvf(s) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -2741,6 +2757,7 @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
     return opfv_widen_check(s, a) &&
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
+           require_scale_zve32f(s) &&
            require_scale_zve64f(s);
 }
 
@@ -2793,6 +2810,7 @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
            vext_check_isa_ill(s) &&
            /* OPFV widening instructions ignore vs1 check */
            vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve32f(s) &&
            require_scale_zve64f(s);
 }
 
-- 
2.31.1



^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
                   ` (14 preceding siblings ...)
  2022-01-18  1:45 ` [PATCH v2 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns frank.chang
@ 2022-01-18  1:45 ` frank.chang
  2022-01-18  1:45 ` [PATCH v2 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on frank.chang
  2022-01-18 22:25 ` [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions Alistair Francis
  17 siblings, 0 replies; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, Frank Chang, Bin Meng, Richard Henderson,
	Alistair Francis, Palmer Dabbelt, LIU Zhiwei

From: Frank Chang <frank.chang@sifive.com>

Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index f2d3c9e8b9..7a040b3089 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2862,6 +2862,7 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
     return opfv_narrow_check(s, a) &&
            require_rvf(s) &&
            (s->sew != MO_64) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -2870,6 +2871,7 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
     return opfv_narrow_check(s, a) &&
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
+           require_scale_zve32f(s) &&
            require_scale_zve64f(s);
 }
 
@@ -2920,6 +2922,7 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
            vext_check_isa_ill(s) &&
            /* OPFV narrowing instructions ignore vs1 check */
            vext_check_sd(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve32f(s) &&
            require_scale_zve64f(s);
 }
 
-- 
2.31.1



^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH v2 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
                   ` (15 preceding siblings ...)
  2022-01-18  1:45 ` [PATCH v2 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing " frank.chang
@ 2022-01-18  1:45 ` frank.chang
  2022-01-18 22:25 ` [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions Alistair Francis
  17 siblings, 0 replies; 20+ messages in thread
From: frank.chang @ 2022-01-18  1:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: Frank Chang, Alistair Francis, Bin Meng, qemu-riscv,
	Palmer Dabbelt

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0898954c02..33c1df638b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -664,6 +664,7 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
     DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
     DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
+    DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
     DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
-- 
2.31.1



^ permalink raw reply related	[flat|nested] 20+ messages in thread

* Re: [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions
  2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
                   ` (16 preceding siblings ...)
  2022-01-18  1:45 ` [PATCH v2 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on frank.chang
@ 2022-01-18 22:25 ` Alistair Francis
  17 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2022-01-18 22:25 UTC (permalink / raw)
  To: Frank Chang; +Cc: open list:RISC-V, qemu-devel@nongnu.org Developers

On Tue, Jan 18, 2022 at 11:50 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> In RVV v1.0 spec, several Zve* vector extensions for embedded processors
> are defined in Chapter 18.2:
> https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#zve-vector-extensions-for-embedded-processors
>
> This patchset implements Zve32f and Zve64f extensions.
>
> The port is available at:
> https://github.com/sifive/qemu/tree/rvv-zve32f-zve64f-upstream-v2
>
> Zve32f can be enabled with -cpu option: Zve32f=true and
> Zve64f can be enabled with -cpu option: Zve64f=true.
> V is not required to be enabled explicitly.
>
> Here's the inclusion diagram for the six standard vector extensions
> quoted from Nick Knight <nick.knight@sifive.com>:
>
>       V
>       |
>     Zve64d
>       |
>     Zve64f
>    /      \
> Zve64x   Zve32f
>    \      /
>     Zve32x
>
> Changelog:
>
> v2:
>   * Replace hardcoded TARGET_RISCV32 macro with get_xl().
>
> Frank Chang (17):
>   target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
>   target/riscv: rvv-1.0: Add Zve64f support for configuration insns
>   target/riscv: rvv-1.0: Add Zve64f support for load and store insns
>   target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
>   target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx
>     insns
>   target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
>   target/riscv: rvv-1.0: Add Zve64f support for single-width fp
>     reduction insns
>   target/riscv: rvv-1.0: Add Zve64f support for widening type-convert
>     insns
>   target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert
>     insns
>   target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
>   target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
>   target/riscv: rvv-1.0: Add Zve32f support for configuration insns
>   target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
>   target/riscv: rvv-1.0: Add Zve32f support for single-width fp
>     reduction insns
>   target/riscv: rvv-1.0: Add Zve32f support for widening type-convert
>     insns
>   target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert
>     insns
>   target/riscv: rvv-1.0: Allow Zve32f extension to be turned on

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c                      |   6 +
>  target/riscv/cpu.h                      |   2 +
>  target/riscv/cpu_helper.c               |   5 +-
>  target/riscv/csr.c                      |   6 +-
>  target/riscv/insn_trans/trans_rvv.c.inc | 219 ++++++++++++++++++++----
>  target/riscv/translate.c                |   4 +
>  6 files changed, 205 insertions(+), 37 deletions(-)
>
> --
> 2.31.1
>
>


^ permalink raw reply	[flat|nested] 20+ messages in thread

end of thread, other threads:[~2022-01-18 22:27 UTC | newest]

Thread overview: 20+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-01-18  1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
2022-01-18  1:45 ` [PATCH v2 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V frank.chang
2022-01-18  1:45 ` [PATCH v2 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns frank.chang
2022-01-18  1:45 ` [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns frank.chang
2022-01-18  4:42   ` Alistair Francis
2022-01-18  1:45 ` [PATCH v2 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns frank.chang
2022-01-18  1:45 ` [PATCH v2 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns frank.chang
2022-01-18  1:45 ` [PATCH v2 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns frank.chang
2022-01-18  1:45 ` [PATCH v2 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns frank.chang
2022-01-18  1:45 ` [PATCH v2 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns frank.chang
2022-01-18  1:45 ` [PATCH v2 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing " frank.chang
2022-01-18  1:45 ` [PATCH v2 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on frank.chang
2022-01-18  1:45 ` [PATCH v2 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V frank.chang
2022-01-18  1:45 ` [PATCH v2 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns frank.chang
2022-01-18  1:45 ` [PATCH v2 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns frank.chang
2022-01-18  1:45 ` [PATCH v2 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns frank.chang
2022-01-18  1:45 ` [PATCH v2 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns frank.chang
2022-01-18  1:45 ` [PATCH v2 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing " frank.chang
2022-01-18  1:45 ` [PATCH v2 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on frank.chang
2022-01-18 22:25 ` [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions Alistair Francis

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