From: Alistair Francis <alistair23@gmail.com>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: qemu-devel@nongnu.org, "Weiwei Li" <liwei1518@gmail.com>,
"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
"Warner Losh" <imp@bsdimp.com>,
"Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>,
"Vijai Kumar K" <vijai@behindbytes.com>,
"Anton Johansson" <anjo@rev.ng>,
"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
qemu-riscv@nongnu.org,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
"Djordje Todorovic" <Djordje.Todorovic@htecgroup.com>
Subject: Re: [PATCH-for-11.1 05/16] target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again)
Date: Thu, 26 Mar 2026 12:07:42 +1000 [thread overview]
Message-ID: <CAKmqyKMkeZWrCoCcNKoONXuc6-9AxqdTPJAnRK_Q4aSBjuc1gw@mail.gmail.com> (raw)
In-Reply-To: <20260318103122.97244-6-philmd@linaro.org>
On Wed, Mar 18, 2026 at 8:33 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Following commit 73ae67fd4e6, extract the implicit MO_TE
> definition in order to replace it.
>
> Mechanical change using:
>
> $ for n in UW UL UQ UO SW SL SQ; do \
> sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
> $(git grep -l MO_TE$n target/riscv); \
> done
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvzalasr.c.inc | 12 ++++++------
> target/riscv/insn_trans/trans_xmips.c.inc | 16 ++++++++--------
> target/riscv/insn_trans/trans_zilsd.c.inc | 4 ++--
> 3 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/insn_trans/trans_rvzalasr.c.inc
> index bf86805cef6..525f01ca347 100644
> --- a/target/riscv/insn_trans/trans_rvzalasr.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc
> @@ -49,20 +49,20 @@ static bool trans_lb_aqrl(DisasContext *ctx, arg_lb_aqrl *a)
> static bool trans_lh_aqrl(DisasContext *ctx, arg_lh_aqrl *a)
> {
> REQUIRE_ZALASR(ctx);
> - return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESW));
> + return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
> }
>
> static bool trans_lw_aqrl(DisasContext *ctx, arg_lw_aqrl *a)
> {
> REQUIRE_ZALASR(ctx);
> - return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESL));
> + return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
> }
>
> static bool trans_ld_aqrl(DisasContext *ctx, arg_ld_aqrl *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_ZALASR(ctx);
> - return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TEUQ));
> + return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
> }
>
> static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
> @@ -96,18 +96,18 @@ static bool trans_sb_aqrl(DisasContext *ctx, arg_sb_aqrl *a)
> static bool trans_sh_aqrl(DisasContext *ctx, arg_sh_aqrl *a)
> {
> REQUIRE_ZALASR(ctx);
> - return gen_store_release(ctx, a, (MO_ALIGN | MO_TESW));
> + return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
> }
>
> static bool trans_sw_aqrl(DisasContext *ctx, arg_sw_aqrl *a)
> {
> REQUIRE_ZALASR(ctx);
> - return gen_store_release(ctx, a, (MO_ALIGN | MO_TESL));
> + return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
> }
>
> static bool trans_sd_aqrl(DisasContext *ctx, arg_sd_aqrl *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_ZALASR(ctx);
> - return gen_store_release(ctx, a, (MO_ALIGN | MO_TEUQ));
> + return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
> }
> diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_trans/trans_xmips.c.inc
> index 9a72f3392f1..37572563ae9 100644
> --- a/target/riscv/insn_trans/trans_xmips.c.inc
> +++ b/target/riscv/insn_trans/trans_xmips.c.inc
> @@ -56,11 +56,11 @@ static bool trans_ldp(DisasContext *ctx, arg_ldp *a)
> TCGv addr = tcg_temp_new();
>
> tcg_gen_addi_tl(addr, src, a->imm_y);
> - tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESQ);
> + tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SQ);
> gen_set_gpr(ctx, a->rd, dest0);
>
> tcg_gen_addi_tl(addr, addr, 8);
> - tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESQ);
> + tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SQ);
> gen_set_gpr(ctx, a->rs3, dest1);
>
> return true;
> @@ -77,11 +77,11 @@ static bool trans_lwp(DisasContext *ctx, arg_lwp *a)
> TCGv addr = tcg_temp_new();
>
> tcg_gen_addi_tl(addr, src, a->imm_x);
> - tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESL);
> + tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SL);
> gen_set_gpr(ctx, a->rd, dest0);
>
> tcg_gen_addi_tl(addr, addr, 4);
> - tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESL);
> + tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SL);
> gen_set_gpr(ctx, a->rs3, dest1);
>
> return true;
> @@ -99,10 +99,10 @@ static bool trans_sdp(DisasContext *ctx, arg_sdp *a)
> TCGv addr = tcg_temp_new();
>
> tcg_gen_addi_tl(addr, src, a->imm_w);
> - tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TEUQ);
> + tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_UQ);
>
> tcg_gen_addi_tl(addr, addr, 8);
> - tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TEUQ);
> + tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_UQ);
>
> return true;
> }
> @@ -118,10 +118,10 @@ static bool trans_swp(DisasContext *ctx, arg_swp *a)
> TCGv addr = tcg_temp_new();
>
> tcg_gen_addi_tl(addr, src, a->imm_v);
> - tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TESL);
> + tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_SL);
>
> tcg_gen_addi_tl(addr, addr, 4);
> - tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TESL);
> + tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_SL);
>
> return true;
> }
> diff --git a/target/riscv/insn_trans/trans_zilsd.c.inc b/target/riscv/insn_trans/trans_zilsd.c.inc
> index 369c33004b6..445406cf015 100644
> --- a/target/riscv/insn_trans/trans_zilsd.c.inc
> +++ b/target/riscv/insn_trans/trans_zilsd.c.inc
> @@ -30,7 +30,7 @@ static bool gen_load_i64(DisasContext *ctx, arg_ld *a)
> TCGv addr = get_address(ctx, a->rs1, a->imm);
> TCGv_i64 tmp = tcg_temp_new_i64();
>
> - tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TESQ);
> + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
>
> if (a->rd == 0) {
> return true;
> @@ -85,7 +85,7 @@ static bool gen_store_i64(DisasContext *ctx, arg_sd *a)
> } else {
> tcg_gen_concat_tl_i64(tmp, data_low, data_high);
> }
> - tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TESQ);
> + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
>
> return true;
> }
> --
> 2.53.0
>
>
next prev parent reply other threads:[~2026-03-26 2:08 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
2026-03-18 10:31 ` [PATCH-for-11.1 01/16] hw/riscv: Mark RISC-V specific peripherals as little-endian Philippe Mathieu-Daudé
2026-03-19 1:43 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 02/16] target/riscv: Use explicit little-endian LD/ST API Philippe Mathieu-Daudé
2026-03-19 3:09 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 03/16] target/riscv: Make LQ and SQ use 128-bit ld/st Philippe Mathieu-Daudé
2026-03-26 2:06 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 04/16] target/riscv: Remove MTTCG check for x-rv128 CPU model Philippe Mathieu-Daudé
2026-03-26 2:06 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 05/16] target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again) Philippe Mathieu-Daudé
2026-03-26 2:07 ` Alistair Francis [this message]
2026-03-18 10:31 ` [PATCH-for-11.1 06/16] target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / store_release Philippe Mathieu-Daudé
2026-03-26 2:08 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 07/16] target/riscv: Factor tiny ldn() helper in gdbstub Philippe Mathieu-Daudé
2026-03-26 2:09 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 08/16] target/riscv: Simplify riscv_cpu_gdb_write_register() Philippe Mathieu-Daudé
2026-03-26 2:12 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 09/16] target/riscv: Expose mo_endian_env() Philippe Mathieu-Daudé
2026-03-26 2:13 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 10/16] target/riscv: Have gdbstub consider CPU endianness Philippe Mathieu-Daudé
2026-03-26 2:15 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 11/16] target/riscv: Replace MO_TE by mo_endian (MIPS extension) Philippe Mathieu-Daudé
2026-03-26 2:17 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 12/16] target/riscv: Replace MO_TE by mo_endian (Zilsd extension) Philippe Mathieu-Daudé
2026-03-26 2:18 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 13/16] target/riscv: Replace MO_TE by mo_endian (Zalasr extension) Philippe Mathieu-Daudé
2026-03-26 2:20 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 14/16] target/riscv: Replace MO_TE -> MO_LE Philippe Mathieu-Daudé
2026-03-26 2:21 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 15/16] target/riscv: Use MO_LE for instruction fetch Philippe Mathieu-Daudé
2026-03-20 11:27 ` Djordje Todorovic
2026-03-18 10:31 ` [PATCH-for-11.1 16/16] configs/targets: Forbid RISC-V to use legacy native endianness APIs Philippe Mathieu-Daudé
2026-03-26 2:21 ` Alistair Francis
2026-03-26 2:28 ` [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Alistair Francis
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