* [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API
@ 2026-03-18 10:31 Philippe Mathieu-Daudé
2026-03-18 10:31 ` [PATCH-for-11.1 01/16] hw/riscv: Mark RISC-V specific peripherals as little-endian Philippe Mathieu-Daudé
` (16 more replies)
0 siblings, 17 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-03-18 10:31 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell,
Philippe Mathieu-Daudé, Alistair Francis, Liu Zhiwei,
Djordje Todorovic
Thanks to Frédéric patch on 128-bit registers, we can now
remove all legacy native endianness API uses of RISC-V.
Djordje: You should (re)base your "Add RISC-V big-endian
target support" [*] series on this (after addressing the
review comments) before posting your v4.
[*] https://lore.kernel.org/qemu-devel/20260311115910.564481-1-djordje.todorovic@htecgroup.com/
Djordje Todorovic (1):
target/riscv: Use MO_LE for instruction fetch
Frédéric Pétrot (2):
target/riscv: Make LQ and SQ use 128-bit ld/st
target/riscv: Remove MTTCG check for x-rv128 CPU model
Philippe Mathieu-Daudé (13):
hw/riscv: Mark RISC-V specific peripherals as little-endian
target/riscv: Use explicit little-endian LD/ST API
target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again)
target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire /
store_release
target/riscv: Factor tiny ldn() helper in gdbstub
target/riscv: Simplify riscv_cpu_gdb_write_register()
target/riscv: Expose mo_endian_env()
target/riscv: Have gdbstub consider CPU endianness
target/riscv: Replace MO_TE by mo_endian (MIPS extension)
target/riscv: Replace MO_TE by mo_endian (Zilsd extension)
target/riscv: Replace MO_TE by mo_endian (Zalasr extension)
target/riscv: Replace MO_TE -> MO_LE
configs/targets: Forbid RISC-V to use legacy native endianness APIs
configs/targets/riscv32-linux-user.mak | 1 +
configs/targets/riscv32-softmmu.mak | 1 +
configs/targets/riscv64-bsd-user.mak | 1 +
configs/targets/riscv64-linux-user.mak | 1 +
configs/targets/riscv64-softmmu.mak | 1 +
target/riscv/internals.h | 12 ++++++
hw/char/ibex_uart.c | 2 +-
hw/char/shakti_uart.c | 2 +-
hw/char/sifive_uart.c | 2 +-
hw/misc/sifive_e_aon.c | 2 +-
hw/misc/sifive_e_prci.c | 2 +-
hw/misc/sifive_u_otp.c | 2 +-
hw/misc/sifive_u_prci.c | 2 +-
hw/riscv/riscv-iommu.c | 2 +-
hw/sd/cadence_sdhci.c | 2 +-
hw/timer/ibex_timer.c | 2 +-
hw/timer/sifive_pwm.c | 2 +-
target/riscv/cpu_helper.c | 4 +-
target/riscv/gdbstub.c | 42 ++++++++------------
target/riscv/op_helper.c | 14 -------
target/riscv/tcg/tcg-cpu.c | 10 -----
target/riscv/translate.c | 10 ++---
target/riscv/insn_trans/trans_rvi.c.inc | 32 +++++++++++----
target/riscv/insn_trans/trans_rvzalasr.c.inc | 18 +++++----
target/riscv/insn_trans/trans_xmips.c.inc | 24 +++++++----
target/riscv/insn_trans/trans_zilsd.c.inc | 4 +-
26 files changed, 104 insertions(+), 93 deletions(-)
--
2.53.0
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH-for-11.1 01/16] hw/riscv: Mark RISC-V specific peripherals as little-endian
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
@ 2026-03-18 10:31 ` Philippe Mathieu-Daudé
2026-03-19 1:43 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 02/16] target/riscv: Use explicit little-endian LD/ST API Philippe Mathieu-Daudé
` (15 subsequent siblings)
16 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-03-18 10:31 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell,
Philippe Mathieu-Daudé, Alistair Francis, Liu Zhiwei,
Djordje Todorovic, Marc-André Lureau, Paolo Bonzini,
Edgar E. Iglesias, qemu-arm
These devices are only used by the RISC-V targets, which are
only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN
definition expand to DEVICE_LITTLE_ENDIAN (besides, the
DEVICE_BIG_ENDIAN case isn't tested). Simplify directly
using DEVICE_LITTLE_ENDIAN.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/char/ibex_uart.c | 2 +-
hw/char/shakti_uart.c | 2 +-
hw/char/sifive_uart.c | 2 +-
hw/misc/sifive_e_aon.c | 2 +-
hw/misc/sifive_e_prci.c | 2 +-
hw/misc/sifive_u_otp.c | 2 +-
hw/misc/sifive_u_prci.c | 2 +-
hw/riscv/riscv-iommu.c | 2 +-
hw/sd/cadence_sdhci.c | 2 +-
hw/timer/ibex_timer.c | 2 +-
hw/timer/sifive_pwm.c | 2 +-
11 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
index 127d219df3c..26ed1aea140 100644
--- a/hw/char/ibex_uart.c
+++ b/hw/char/ibex_uart.c
@@ -470,7 +470,7 @@ static void fifo_trigger_update(void *opaque)
static const MemoryRegionOps ibex_uart_ops = {
.read = ibex_uart_read,
.write = ibex_uart_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl.min_access_size = 4,
.impl.max_access_size = 4,
};
diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c
index 2d1bc9cb8e2..d38920a03a0 100644
--- a/hw/char/shakti_uart.c
+++ b/hw/char/shakti_uart.c
@@ -103,7 +103,7 @@ static void shakti_uart_write(void *opaque, hwaddr addr,
static const MemoryRegionOps shakti_uart_ops = {
.read = shakti_uart_read,
.write = shakti_uart_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl = {.min_access_size = 1, .max_access_size = 4},
.valid = {.min_access_size = 1, .max_access_size = 4},
};
diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
index af17cf9a6ce..4e31842df5c 100644
--- a/hw/char/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -206,7 +206,7 @@ static void fifo_trigger_update(void *opaque)
static const MemoryRegionOps sifive_uart_ops = {
.read = sifive_uart_read,
.write = sifive_uart_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4
diff --git a/hw/misc/sifive_e_aon.c b/hw/misc/sifive_e_aon.c
index e78f4f56725..ff2a7c18235 100644
--- a/hw/misc/sifive_e_aon.c
+++ b/hw/misc/sifive_e_aon.c
@@ -250,7 +250,7 @@ sifive_e_aon_write(void *opaque, hwaddr addr,
static const MemoryRegionOps sifive_e_aon_ops = {
.read = sifive_e_aon_read,
.write = sifive_e_aon_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 4,
.max_access_size = 4
diff --git a/hw/misc/sifive_e_prci.c b/hw/misc/sifive_e_prci.c
index 400664aabae..a4a60e7b406 100644
--- a/hw/misc/sifive_e_prci.c
+++ b/hw/misc/sifive_e_prci.c
@@ -75,7 +75,7 @@ static void sifive_e_prci_write(void *opaque, hwaddr addr,
static const MemoryRegionOps sifive_e_prci_ops = {
.read = sifive_e_prci_read,
.write = sifive_e_prci_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
index 7205374bc39..cececd4f7a8 100644
--- a/hw/misc/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -187,7 +187,7 @@ static void sifive_u_otp_write(void *opaque, hwaddr addr,
static const MemoryRegionOps sifive_u_otp_ops = {
.read = sifive_u_otp_read,
.write = sifive_u_otp_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4
diff --git a/hw/misc/sifive_u_prci.c b/hw/misc/sifive_u_prci.c
index f51588623ab..4674d5925ea 100644
--- a/hw/misc/sifive_u_prci.c
+++ b/hw/misc/sifive_u_prci.c
@@ -112,7 +112,7 @@ static void sifive_u_prci_write(void *opaque, hwaddr addr,
static const MemoryRegionOps sifive_u_prci_ops = {
.read = sifive_u_prci_read,
.write = sifive_u_prci_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 98345b1280b..ef5d7df2385 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -2375,7 +2375,7 @@ static MemTxResult riscv_iommu_mmio_read(void *opaque, hwaddr addr,
static const MemoryRegionOps riscv_iommu_mmio_ops = {
.read_with_attrs = riscv_iommu_mmio_read,
.write_with_attrs = riscv_iommu_mmio_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 4,
.max_access_size = 8,
diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c
index d576855a1a8..8476baf67fb 100644
--- a/hw/sd/cadence_sdhci.c
+++ b/hw/sd/cadence_sdhci.c
@@ -122,7 +122,7 @@ static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
static const MemoryRegionOps cadence_sdhci_ops = {
.read = cadence_sdhci_read,
.write = cadence_sdhci_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
index ee186521893..0f12531934d 100644
--- a/hw/timer/ibex_timer.c
+++ b/hw/timer/ibex_timer.c
@@ -234,7 +234,7 @@ static void ibex_timer_write(void *opaque, hwaddr addr,
static const MemoryRegionOps ibex_timer_ops = {
.read = ibex_timer_read,
.write = ibex_timer_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
.impl.min_access_size = 4,
.impl.max_access_size = 4,
};
diff --git a/hw/timer/sifive_pwm.c b/hw/timer/sifive_pwm.c
index 780eaa50799..4f4f566cd4b 100644
--- a/hw/timer/sifive_pwm.c
+++ b/hw/timer/sifive_pwm.c
@@ -388,7 +388,7 @@ static void sifive_pwm_reset(DeviceState *dev)
static const MemoryRegionOps sifive_pwm_ops = {
.read = sifive_pwm_read,
.write = sifive_pwm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static const VMStateDescription vmstate_sifive_pwm = {
--
2.53.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH-for-11.1 02/16] target/riscv: Use explicit little-endian LD/ST API
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
2026-03-18 10:31 ` [PATCH-for-11.1 01/16] hw/riscv: Mark RISC-V specific peripherals as little-endian Philippe Mathieu-Daudé
@ 2026-03-18 10:31 ` Philippe Mathieu-Daudé
2026-03-19 3:09 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 03/16] target/riscv: Make LQ and SQ use 128-bit ld/st Philippe Mathieu-Daudé
` (14 subsequent siblings)
16 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-03-18 10:31 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell,
Philippe Mathieu-Daudé, Alistair Francis, Liu Zhiwei,
Djordje Todorovic
We only build our RISC-V targets as little-endian, therefore
the LD/ST API expands to its little-endian variant. Directly
use the latter.
Mechanical change running:
$ for a in uw w l q; do \
sed -i -e "s/ld${a}_p(/ld${a}_le_p(/" \
$(git grep -wlE '(ld|st)u?[wlq]_p' target/riscv);
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/cpu_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index dd6c861a90e..c28832e0e39 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1365,9 +1365,9 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
}
if (riscv_cpu_mxl(env) == MXL_RV32) {
- pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
+ pte = address_space_ldl_le(cs->as, pte_addr, attrs, &res);
} else {
- pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
+ pte = address_space_ldq_le(cs->as, pte_addr, attrs, &res);
}
if (res != MEMTX_OK) {
--
2.53.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH-for-11.1 03/16] target/riscv: Make LQ and SQ use 128-bit ld/st
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
2026-03-18 10:31 ` [PATCH-for-11.1 01/16] hw/riscv: Mark RISC-V specific peripherals as little-endian Philippe Mathieu-Daudé
2026-03-18 10:31 ` [PATCH-for-11.1 02/16] target/riscv: Use explicit little-endian LD/ST API Philippe Mathieu-Daudé
@ 2026-03-18 10:31 ` Philippe Mathieu-Daudé
2026-03-26 2:06 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 04/16] target/riscv: Remove MTTCG check for x-rv128 CPU model Philippe Mathieu-Daudé
` (13 subsequent siblings)
16 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-03-18 10:31 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell,
Philippe Mathieu-Daudé, Alistair Francis, Liu Zhiwei,
Djordje Todorovic, Richard Henderson
From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
The lq and sq helpers for the experimental rv128 architecture
currently use direct memory accesses.
Replace these direct accesses with the standard
tcg_gen_qemu_{ld,st}_i128 TCG helpers that handle endianness
issues.
Reported-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Message-ID: <20260101181442.2489496-2-frederic.petrot@univ-grenoble-alpes.fr>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 32 ++++++++++++++++++-------
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 54b9b4f2413..2c82ae41a77 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -377,6 +377,9 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
TCGv destl = dest_gpr(ctx, a->rd);
TCGv desth = dest_gprh(ctx, a->rd);
TCGv addrl = tcg_temp_new();
+ TCGv_i128 t16 = tcg_temp_new_i128();
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 th = tcg_temp_new_i64();
tcg_gen_addi_tl(addrl, src1l, a->imm);
@@ -388,10 +391,14 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
tcg_gen_movi_tl(desth, 0);
}
} else {
- /* assume little-endian memory access for now */
- tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, MO_TEUQ);
- tcg_gen_addi_tl(addrl, addrl, 8);
- tcg_gen_qemu_ld_tl(desth, addrl, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_ld_i128(t16, addrl, ctx->mem_idx, memop);
+ if (mo_endian(ctx) == MO_LE) {
+ tcg_gen_extr_i128_i64(tl, th, t16);
+ } else {
+ tcg_gen_extr_i128_i64(th, tl, t16);
+ }
+ tcg_gen_trunc_i64_tl(destl, tl);
+ tcg_gen_trunc_i64_tl(desth, th);
}
gen_set_gpr128(ctx, a->rd, destl, desth);
@@ -488,16 +495,25 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)
TCGv src2l = get_gpr(ctx, a->rs2, EXT_NONE);
TCGv src2h = get_gprh(ctx, a->rs2);
TCGv addrl = tcg_temp_new();
+ TCGv_i128 t16 = tcg_temp_new_i128();
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 th = tcg_temp_new_i64();
tcg_gen_addi_tl(addrl, src1l, a->imm);
if ((memop & MO_SIZE) <= MO_64) {
tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop);
} else {
- /* little-endian memory access assumed for now */
- tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, MO_TEUQ);
- tcg_gen_addi_tl(addrl, addrl, 8);
- tcg_gen_qemu_st_tl(src2h, addrl, ctx->mem_idx, MO_TEUQ);
+
+ tcg_gen_ext_tl_i64(tl, src2l);
+ tcg_gen_ext_tl_i64(th, src2h);
+
+ if (mo_endian(ctx) == MO_LE) {
+ tcg_gen_concat_i64_i128(t16, tl, th);
+ } else {
+ tcg_gen_concat_i64_i128(t16, th, tl);
+ }
+ tcg_gen_qemu_st_i128(t16, addrl, ctx->mem_idx, memop);
}
return true;
}
--
2.53.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH-for-11.1 04/16] target/riscv: Remove MTTCG check for x-rv128 CPU model
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2026-03-18 10:31 ` [PATCH-for-11.1 03/16] target/riscv: Make LQ and SQ use 128-bit ld/st Philippe Mathieu-Daudé
@ 2026-03-18 10:31 ` Philippe Mathieu-Daudé
2026-03-26 2:06 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 05/16] target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again) Philippe Mathieu-Daudé
` (12 subsequent siblings)
16 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-03-18 10:31 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell,
Philippe Mathieu-Daudé, Alistair Francis, Liu Zhiwei,
Djordje Todorovic
From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
We had to check that mttcg was not used when executing QEMU with
-cpu x-rv128 as a single 128-bit access was done as two distinct
64-bit accesses.
Now that we use the 128-bit ld/st that access the data atomically,
this check is no longer necessary.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Message-ID: <20260101181442.2489496-3-frederic.petrot@univ-grenoble-alpes.fr>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/tcg/tcg-cpu.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 988b2d905f5..3407191c224 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -1305,16 +1305,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
}
#ifndef CONFIG_USER_ONLY
- RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
-
- if (mcc->def->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
- /* Missing 128-bit aligned atomics */
- error_setg(errp,
- "128-bit RISC-V currently does not work with Multi "
- "Threaded TCG. Please use: -accel tcg,thread=single");
- return false;
- }
-
CPURISCVState *env = &cpu->env;
tcg_cflags_set(CPU(cs), CF_PCREL);
--
2.53.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH-for-11.1 05/16] target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again)
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2026-03-18 10:31 ` [PATCH-for-11.1 04/16] target/riscv: Remove MTTCG check for x-rv128 CPU model Philippe Mathieu-Daudé
@ 2026-03-18 10:31 ` Philippe Mathieu-Daudé
2026-03-26 2:07 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 06/16] target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / store_release Philippe Mathieu-Daudé
` (11 subsequent siblings)
16 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-03-18 10:31 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell,
Philippe Mathieu-Daudé, Alistair Francis, Liu Zhiwei,
Djordje Todorovic
Following commit 73ae67fd4e6, extract the implicit MO_TE
definition in order to replace it.
Mechanical change using:
$ for n in UW UL UQ UO SW SL SQ; do \
sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
$(git grep -l MO_TE$n target/riscv); \
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/insn_trans/trans_rvzalasr.c.inc | 12 ++++++------
target/riscv/insn_trans/trans_xmips.c.inc | 16 ++++++++--------
target/riscv/insn_trans/trans_zilsd.c.inc | 4 ++--
3 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/insn_trans/trans_rvzalasr.c.inc
index bf86805cef6..525f01ca347 100644
--- a/target/riscv/insn_trans/trans_rvzalasr.c.inc
+++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc
@@ -49,20 +49,20 @@ static bool trans_lb_aqrl(DisasContext *ctx, arg_lb_aqrl *a)
static bool trans_lh_aqrl(DisasContext *ctx, arg_lh_aqrl *a)
{
REQUIRE_ZALASR(ctx);
- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESW));
+ return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
}
static bool trans_lw_aqrl(DisasContext *ctx, arg_lw_aqrl *a)
{
REQUIRE_ZALASR(ctx);
- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESL));
+ return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
}
static bool trans_ld_aqrl(DisasContext *ctx, arg_ld_aqrl *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZALASR(ctx);
- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TEUQ));
+ return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
}
static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
@@ -96,18 +96,18 @@ static bool trans_sb_aqrl(DisasContext *ctx, arg_sb_aqrl *a)
static bool trans_sh_aqrl(DisasContext *ctx, arg_sh_aqrl *a)
{
REQUIRE_ZALASR(ctx);
- return gen_store_release(ctx, a, (MO_ALIGN | MO_TESW));
+ return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
}
static bool trans_sw_aqrl(DisasContext *ctx, arg_sw_aqrl *a)
{
REQUIRE_ZALASR(ctx);
- return gen_store_release(ctx, a, (MO_ALIGN | MO_TESL));
+ return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
}
static bool trans_sd_aqrl(DisasContext *ctx, arg_sd_aqrl *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZALASR(ctx);
- return gen_store_release(ctx, a, (MO_ALIGN | MO_TEUQ));
+ return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
}
diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_trans/trans_xmips.c.inc
index 9a72f3392f1..37572563ae9 100644
--- a/target/riscv/insn_trans/trans_xmips.c.inc
+++ b/target/riscv/insn_trans/trans_xmips.c.inc
@@ -56,11 +56,11 @@ static bool trans_ldp(DisasContext *ctx, arg_ldp *a)
TCGv addr = tcg_temp_new();
tcg_gen_addi_tl(addr, src, a->imm_y);
- tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESQ);
+ tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SQ);
gen_set_gpr(ctx, a->rd, dest0);
tcg_gen_addi_tl(addr, addr, 8);
- tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESQ);
+ tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SQ);
gen_set_gpr(ctx, a->rs3, dest1);
return true;
@@ -77,11 +77,11 @@ static bool trans_lwp(DisasContext *ctx, arg_lwp *a)
TCGv addr = tcg_temp_new();
tcg_gen_addi_tl(addr, src, a->imm_x);
- tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESL);
+ tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SL);
gen_set_gpr(ctx, a->rd, dest0);
tcg_gen_addi_tl(addr, addr, 4);
- tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESL);
+ tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SL);
gen_set_gpr(ctx, a->rs3, dest1);
return true;
@@ -99,10 +99,10 @@ static bool trans_sdp(DisasContext *ctx, arg_sdp *a)
TCGv addr = tcg_temp_new();
tcg_gen_addi_tl(addr, src, a->imm_w);
- tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_UQ);
tcg_gen_addi_tl(addr, addr, 8);
- tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_UQ);
return true;
}
@@ -118,10 +118,10 @@ static bool trans_swp(DisasContext *ctx, arg_swp *a)
TCGv addr = tcg_temp_new();
tcg_gen_addi_tl(addr, src, a->imm_v);
- tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TESL);
+ tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_SL);
tcg_gen_addi_tl(addr, addr, 4);
- tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TESL);
+ tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_SL);
return true;
}
diff --git a/target/riscv/insn_trans/trans_zilsd.c.inc b/target/riscv/insn_trans/trans_zilsd.c.inc
index 369c33004b6..445406cf015 100644
--- a/target/riscv/insn_trans/trans_zilsd.c.inc
+++ b/target/riscv/insn_trans/trans_zilsd.c.inc
@@ -30,7 +30,7 @@ static bool gen_load_i64(DisasContext *ctx, arg_ld *a)
TCGv addr = get_address(ctx, a->rs1, a->imm);
TCGv_i64 tmp = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TESQ);
+ tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
if (a->rd == 0) {
return true;
@@ -85,7 +85,7 @@ static bool gen_store_i64(DisasContext *ctx, arg_sd *a)
} else {
tcg_gen_concat_tl_i64(tmp, data_low, data_high);
}
- tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TESQ);
+ tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
return true;
}
--
2.53.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH-for-11.1 06/16] target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / store_release
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2026-03-18 10:31 ` [PATCH-for-11.1 05/16] target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again) Philippe Mathieu-Daudé
@ 2026-03-18 10:31 ` Philippe Mathieu-Daudé
2026-03-26 2:08 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 07/16] target/riscv: Factor tiny ldn() helper in gdbstub Philippe Mathieu-Daudé
` (10 subsequent siblings)
16 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-03-18 10:31 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell,
Philippe Mathieu-Daudé, Alistair Francis, Liu Zhiwei,
Djordje Todorovic
All callers of gen_load_acquire() and gen_store_release() set both
the MO_ALIGN|MO_TE flags. Set them once in each callee.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/insn_trans/trans_rvzalasr.c.inc | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/insn_trans/trans_rvzalasr.c.inc
index 525f01ca347..2b1f73f650b 100644
--- a/target/riscv/insn_trans/trans_rvzalasr.c.inc
+++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc
@@ -29,6 +29,7 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)
return false;
}
+ memop |= MO_ALIGN | MO_TE;
memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
@@ -43,26 +44,26 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)
static bool trans_lb_aqrl(DisasContext *ctx, arg_lb_aqrl *a)
{
REQUIRE_ZALASR(ctx);
- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_SB));
+ return gen_load_acquire(ctx, a, MO_SB);
}
static bool trans_lh_aqrl(DisasContext *ctx, arg_lh_aqrl *a)
{
REQUIRE_ZALASR(ctx);
- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
+ return gen_load_acquire(ctx, a, MO_SW);
}
static bool trans_lw_aqrl(DisasContext *ctx, arg_lw_aqrl *a)
{
REQUIRE_ZALASR(ctx);
- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
+ return gen_load_acquire(ctx, a, MO_SL);
}
static bool trans_ld_aqrl(DisasContext *ctx, arg_ld_aqrl *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZALASR(ctx);
- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
+ return gen_load_acquire(ctx, a, MO_UQ);
}
static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
@@ -78,6 +79,7 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
return false;
}
+ memop |= MO_ALIGN | MO_TE;
memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
/* Add a memory barrier implied by RL (mandatory) and AQ (optional) */
@@ -90,24 +92,24 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
static bool trans_sb_aqrl(DisasContext *ctx, arg_sb_aqrl *a)
{
REQUIRE_ZALASR(ctx);
- return gen_store_release(ctx, a, (MO_ALIGN | MO_SB));
+ return gen_store_release(ctx, a, MO_SB);
}
static bool trans_sh_aqrl(DisasContext *ctx, arg_sh_aqrl *a)
{
REQUIRE_ZALASR(ctx);
- return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
+ return gen_store_release(ctx, a, MO_SW);
}
static bool trans_sw_aqrl(DisasContext *ctx, arg_sw_aqrl *a)
{
REQUIRE_ZALASR(ctx);
- return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
+ return gen_store_release(ctx, a, MO_SL);
}
static bool trans_sd_aqrl(DisasContext *ctx, arg_sd_aqrl *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZALASR(ctx);
- return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
+ return gen_store_release(ctx, a, MO_UQ);
}
--
2.53.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH-for-11.1 07/16] target/riscv: Factor tiny ldn() helper in gdbstub
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2026-03-18 10:31 ` [PATCH-for-11.1 06/16] target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / store_release Philippe Mathieu-Daudé
@ 2026-03-18 10:31 ` Philippe Mathieu-Daudé
2026-03-26 2:09 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 08/16] target/riscv: Simplify riscv_cpu_gdb_write_register() Philippe Mathieu-Daudé
` (9 subsequent siblings)
16 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-03-18 10:31 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell,
Philippe Mathieu-Daudé, Alistair Francis, Liu Zhiwei,
Djordje Todorovic
In preparation of having this helper handle CPU runtime
endianness changes, factor the ldn() helper out.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/gdbstub.c | 22 +++++++++++++---------
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 6a5b7a82fd4..be42566bcc8 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -47,6 +47,11 @@ static const struct TypeSize vec_lanes[] = {
{ "uint8", "bytes", 8, 'b' },
};
+static uint64_t ldn(CPURISCVState *env, uint8_t *mem_buf, size_t regsz)
+{
+ return ldn_p(mem_buf, regsz);
+}
+
int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
@@ -84,15 +89,15 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
switch (mcc->def->misa_mxl_max) {
case MXL_RV32:
- tmp = (int32_t)ldl_p(mem_buf);
+ tmp = (int32_t)ldn(env, mem_buf, 4);
length = 4;
break;
case MXL_RV64:
case MXL_RV128:
if (env->xl < MXL_RV64) {
- tmp = (int32_t)ldq_p(mem_buf);
+ tmp = (int32_t)ldn(env, mem_buf, 8);
} else {
- tmp = ldq_p(mem_buf);
+ tmp = ldn(env, mem_buf, 8);
}
length = 8;
break;
@@ -130,7 +135,7 @@ static int riscv_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n)
CPURISCVState *env = &cpu->env;
if (n < 32) {
- env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
+ env->fpr[n] = ldn(env, mem_buf, 8); /* always 64-bit */
return sizeof(uint64_t);
}
return 0;
@@ -162,7 +167,7 @@ static int riscv_gdb_set_vector(CPUState *cs, uint8_t *mem_buf, int n)
if (n < 32) {
int i;
for (i = 0; i < vlenb; i += 8) {
- env->vreg[(n * vlenb + i) / 8] = ldq_p(mem_buf + i);
+ env->vreg[(n * vlenb + i) / 8] = ldn(env, mem_buf + i, 8);
}
return vlenb;
}
@@ -194,7 +199,7 @@ static int riscv_gdb_set_csr(CPUState *cs, uint8_t *mem_buf, int n)
const unsigned regsz = riscv_cpu_is_32bit(cpu) ? 4 : 8;
if (n < CSR_TABLE_SIZE) {
- uint64_t val = ldn_p(mem_buf, regsz);
+ uint64_t val = ldn(env, mem_buf, regsz);
int result;
result = riscv_csrrw_debug(env, n, NULL, val, -1);
@@ -230,8 +235,7 @@ static int riscv_gdb_set_virtual(CPUState *cs, uint8_t *mem_buf, int n)
const unsigned regsz = riscv_cpu_is_32bit(cpu) ? 4 : 8;
#ifndef CONFIG_USER_ONLY
CPURISCVState *env = &cpu->env;
-
- target_ulong new_priv = ldn_p(mem_buf, regsz) & 0x3;
+ uint64_t new_priv = ldn(env, mem_buf, regsz) & 0x3;
bool new_virt = 0;
if (new_priv == PRV_RESERVED) {
@@ -239,7 +243,7 @@ static int riscv_gdb_set_virtual(CPUState *cs, uint8_t *mem_buf, int n)
}
if (new_priv != PRV_M) {
- new_virt = (ldn_p(mem_buf, regsz) & BIT(2)) >> 2;
+ new_virt = (ldn(env, mem_buf, regsz) & BIT(2)) >> 2;
}
if (riscv_has_ext(env, RVH) && new_virt != env->virt_enabled) {
--
2.53.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH-for-11.1 08/16] target/riscv: Simplify riscv_cpu_gdb_write_register()
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2026-03-18 10:31 ` [PATCH-for-11.1 07/16] target/riscv: Factor tiny ldn() helper in gdbstub Philippe Mathieu-Daudé
@ 2026-03-18 10:31 ` Philippe Mathieu-Daudé
2026-03-26 2:12 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 09/16] target/riscv: Expose mo_endian_env() Philippe Mathieu-Daudé
` (8 subsequent siblings)
16 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-03-18 10:31 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell,
Philippe Mathieu-Daudé, Alistair Francis, Liu Zhiwei,
Djordje Todorovic
Use a single ldn() call, sign-extend once.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
Note I'm skeptical about 128-bit registers path, but this
would be a pre-existing issue.
---
target/riscv/gdbstub.c | 25 ++++++-------------------
1 file changed, 6 insertions(+), 19 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index be42566bcc8..a5c12638782 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -84,33 +84,20 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- int length = 0;
- uint64_t tmp;
+ const size_t regsize = mcc->def->misa_mxl_max == MXL_RV32 ? 4 : 8;
+ uint64_t tmp = ldn(env, mem_buf, regsize);
- switch (mcc->def->misa_mxl_max) {
- case MXL_RV32:
- tmp = (int32_t)ldn(env, mem_buf, 4);
- length = 4;
- break;
- case MXL_RV64:
- case MXL_RV128:
- if (env->xl < MXL_RV64) {
- tmp = (int32_t)ldn(env, mem_buf, 8);
- } else {
- tmp = ldn(env, mem_buf, 8);
- }
- length = 8;
- break;
- default:
- g_assert_not_reached();
+ if (env->xl < MXL_RV64) {
+ tmp = (int32_t)tmp;
}
+
if (n > 0 && n < 32) {
env->gpr[n] = tmp;
} else if (n == 32) {
env->pc = tmp;
}
- return length;
+ return regsize;
}
static int riscv_gdb_get_fpu(CPUState *cs, GByteArray *buf, int n)
--
2.53.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH-for-11.1 09/16] target/riscv: Expose mo_endian_env()
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2026-03-18 10:31 ` [PATCH-for-11.1 08/16] target/riscv: Simplify riscv_cpu_gdb_write_register() Philippe Mathieu-Daudé
@ 2026-03-18 10:31 ` Philippe Mathieu-Daudé
2026-03-26 2:13 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 10/16] target/riscv: Have gdbstub consider CPU endianness Philippe Mathieu-Daudé
` (7 subsequent siblings)
16 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-03-18 10:31 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell,
Philippe Mathieu-Daudé, Alistair Francis, Liu Zhiwei,
Djordje Todorovic
Move mo_endian_env() definition to "internals.h" for re-use.
Do not restrict to system emulation only because this will
also be used by user emulation code.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/internals.h | 12 ++++++++++++
target/riscv/op_helper.c | 14 --------------
2 files changed, 12 insertions(+), 14 deletions(-)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 35b923c4bf5..860c47732b6 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -62,6 +62,18 @@ static inline bool mmuidx_2stage(int mmu_idx)
return mmu_idx & MMU_2STAGE_BIT;
}
+static inline MemOp mo_endian_env(CPURISCVState *env)
+{
+ /*
+ * A couple of bits in MSTATUS set the endianness:
+ * - MSTATUS_UBE (User-mode),
+ * - MSTATUS_SBE (Supervisor-mode),
+ * - MSTATUS_MBE (Machine-mode)
+ * but we don't implement that yet.
+ */
+ return MO_TE;
+}
+
/* share data between vector helpers and decode code */
FIELD(VDATA, VM, 0, 1)
FIELD(VDATA, LMUL, 1, 3)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 6ccc127c304..dde40a55493 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -28,20 +28,6 @@
#include "exec/tlb-flags.h"
#include "trace.h"
-#ifndef CONFIG_USER_ONLY
-static inline MemOp mo_endian_env(CPURISCVState *env)
-{
- /*
- * A couple of bits in MSTATUS set the endianness:
- * - MSTATUS_UBE (User-mode),
- * - MSTATUS_SBE (Supervisor-mode),
- * - MSTATUS_MBE (Machine-mode)
- * but we don't implement that yet.
- */
- return MO_TE;
-}
-#endif
-
/* Exceptions processing helpers */
G_NORETURN void riscv_raise_exception(CPURISCVState *env,
RISCVException exception,
--
2.53.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH-for-11.1 10/16] target/riscv: Have gdbstub consider CPU endianness
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2026-03-18 10:31 ` [PATCH-for-11.1 09/16] target/riscv: Expose mo_endian_env() Philippe Mathieu-Daudé
@ 2026-03-18 10:31 ` Philippe Mathieu-Daudé
2026-03-26 2:15 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 11/16] target/riscv: Replace MO_TE by mo_endian (MIPS extension) Philippe Mathieu-Daudé
` (6 subsequent siblings)
16 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-03-18 10:31 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell,
Philippe Mathieu-Daudé, Alistair Francis, Liu Zhiwei,
Djordje Todorovic
Consider CPU endianness when accessing registers.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/gdbstub.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index a5c12638782..2c6ccd4761c 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -20,6 +20,7 @@
#include "exec/gdbstub.h"
#include "gdbstub/helpers.h"
#include "cpu.h"
+#include "internals.h"
struct TypeSize {
const char *gdb_type;
@@ -49,7 +50,7 @@ static const struct TypeSize vec_lanes[] = {
static uint64_t ldn(CPURISCVState *env, uint8_t *mem_buf, size_t regsz)
{
- return ldn_p(mem_buf, regsz);
+ return (mo_endian_env(env) == MO_LE ? ldn_le_p : ldn_be_p)(mem_buf, regsz);
}
int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
--
2.53.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH-for-11.1 11/16] target/riscv: Replace MO_TE by mo_endian (MIPS extension)
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2026-03-18 10:31 ` [PATCH-for-11.1 10/16] target/riscv: Have gdbstub consider CPU endianness Philippe Mathieu-Daudé
@ 2026-03-18 10:31 ` Philippe Mathieu-Daudé
2026-03-26 2:17 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 12/16] target/riscv: Replace MO_TE by mo_endian (Zilsd extension) Philippe Mathieu-Daudé
` (5 subsequent siblings)
16 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-03-18 10:31 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell,
Philippe Mathieu-Daudé, Alistair Francis, Liu Zhiwei,
Djordje Todorovic
Replace compile-time MO_TE evaluation by runtime mo_endian()
one, which expand target endianness from DisasContext.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/insn_trans/trans_xmips.c.inc | 24 +++++++++++++++--------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_trans/trans_xmips.c.inc
index 37572563ae9..c1a30156d36 100644
--- a/target/riscv/insn_trans/trans_xmips.c.inc
+++ b/target/riscv/insn_trans/trans_xmips.c.inc
@@ -47,6 +47,8 @@ static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a)
/* Load Doubleword Pair. */
static bool trans_ldp(DisasContext *ctx, arg_ldp *a)
{
+ MemOp memop = MO_SQ | mo_endian(ctx);
+
REQUIRE_XMIPSLSP(ctx);
REQUIRE_64_OR_128BIT(ctx);
@@ -56,11 +58,11 @@ static bool trans_ldp(DisasContext *ctx, arg_ldp *a)
TCGv addr = tcg_temp_new();
tcg_gen_addi_tl(addr, src, a->imm_y);
- tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SQ);
+ tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, memop);
gen_set_gpr(ctx, a->rd, dest0);
tcg_gen_addi_tl(addr, addr, 8);
- tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SQ);
+ tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, memop);
gen_set_gpr(ctx, a->rs3, dest1);
return true;
@@ -69,6 +71,8 @@ static bool trans_ldp(DisasContext *ctx, arg_ldp *a)
/* Load Word Pair. */
static bool trans_lwp(DisasContext *ctx, arg_lwp *a)
{
+ MemOp memop = MO_SL | mo_endian(ctx);
+
REQUIRE_XMIPSLSP(ctx);
TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -77,11 +81,11 @@ static bool trans_lwp(DisasContext *ctx, arg_lwp *a)
TCGv addr = tcg_temp_new();
tcg_gen_addi_tl(addr, src, a->imm_x);
- tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SL);
+ tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, memop);
gen_set_gpr(ctx, a->rd, dest0);
tcg_gen_addi_tl(addr, addr, 4);
- tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SL);
+ tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, memop);
gen_set_gpr(ctx, a->rs3, dest1);
return true;
@@ -90,6 +94,8 @@ static bool trans_lwp(DisasContext *ctx, arg_lwp *a)
/* Store Doubleword Pair. */
static bool trans_sdp(DisasContext *ctx, arg_sdp *a)
{
+ MemOp memop = MO_UQ | mo_endian(ctx);
+
REQUIRE_XMIPSLSP(ctx);
REQUIRE_64_OR_128BIT(ctx);
@@ -99,10 +105,10 @@ static bool trans_sdp(DisasContext *ctx, arg_sdp *a)
TCGv addr = tcg_temp_new();
tcg_gen_addi_tl(addr, src, a->imm_w);
- tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, memop);
tcg_gen_addi_tl(addr, addr, 8);
- tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, memop);
return true;
}
@@ -110,6 +116,8 @@ static bool trans_sdp(DisasContext *ctx, arg_sdp *a)
/* Store Word Pair. */
static bool trans_swp(DisasContext *ctx, arg_swp *a)
{
+ MemOp memop = MO_SL | mo_endian(ctx);
+
REQUIRE_XMIPSLSP(ctx);
TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -118,10 +126,10 @@ static bool trans_swp(DisasContext *ctx, arg_swp *a)
TCGv addr = tcg_temp_new();
tcg_gen_addi_tl(addr, src, a->imm_v);
- tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_SL);
+ tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, memop);
tcg_gen_addi_tl(addr, addr, 4);
- tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_SL);
+ tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, memop);
return true;
}
--
2.53.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH-for-11.1 12/16] target/riscv: Replace MO_TE by mo_endian (Zilsd extension)
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2026-03-18 10:31 ` [PATCH-for-11.1 11/16] target/riscv: Replace MO_TE by mo_endian (MIPS extension) Philippe Mathieu-Daudé
@ 2026-03-18 10:31 ` Philippe Mathieu-Daudé
2026-03-26 2:18 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 13/16] target/riscv: Replace MO_TE by mo_endian (Zalasr extension) Philippe Mathieu-Daudé
` (4 subsequent siblings)
16 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-03-18 10:31 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell,
Philippe Mathieu-Daudé, Alistair Francis, Liu Zhiwei,
Djordje Todorovic
Replace compile-time MO_TE evaluation by runtime mo_endian()
one, which expand target endianness from DisasContext.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/insn_trans/trans_zilsd.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_zilsd.c.inc b/target/riscv/insn_trans/trans_zilsd.c.inc
index 445406cf015..f50c52f22c9 100644
--- a/target/riscv/insn_trans/trans_zilsd.c.inc
+++ b/target/riscv/insn_trans/trans_zilsd.c.inc
@@ -30,7 +30,7 @@ static bool gen_load_i64(DisasContext *ctx, arg_ld *a)
TCGv addr = get_address(ctx, a->rs1, a->imm);
TCGv_i64 tmp = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
+ tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx));
if (a->rd == 0) {
return true;
@@ -85,7 +85,7 @@ static bool gen_store_i64(DisasContext *ctx, arg_sd *a)
} else {
tcg_gen_concat_tl_i64(tmp, data_low, data_high);
}
- tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
+ tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx));
return true;
}
--
2.53.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH-for-11.1 13/16] target/riscv: Replace MO_TE by mo_endian (Zalasr extension)
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2026-03-18 10:31 ` [PATCH-for-11.1 12/16] target/riscv: Replace MO_TE by mo_endian (Zilsd extension) Philippe Mathieu-Daudé
@ 2026-03-18 10:31 ` Philippe Mathieu-Daudé
2026-03-26 2:20 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 14/16] target/riscv: Replace MO_TE -> MO_LE Philippe Mathieu-Daudé
` (3 subsequent siblings)
16 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-03-18 10:31 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell,
Philippe Mathieu-Daudé, Alistair Francis, Liu Zhiwei,
Djordje Todorovic
Replace compile-time MO_TE evaluation by runtime mo_endian()
one, which expand target endianness from DisasContext.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/insn_trans/trans_rvzalasr.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/insn_trans/trans_rvzalasr.c.inc
index 2b1f73f650b..0f307affecf 100644
--- a/target/riscv/insn_trans/trans_rvzalasr.c.inc
+++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc
@@ -29,7 +29,7 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)
return false;
}
- memop |= MO_ALIGN | MO_TE;
+ memop |= MO_ALIGN | mo_endian(ctx);
memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
@@ -79,7 +79,7 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
return false;
}
- memop |= MO_ALIGN | MO_TE;
+ memop |= MO_ALIGN | mo_endian(ctx);
memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
/* Add a memory barrier implied by RL (mandatory) and AQ (optional) */
--
2.53.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH-for-11.1 14/16] target/riscv: Replace MO_TE -> MO_LE
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2026-03-18 10:31 ` [PATCH-for-11.1 13/16] target/riscv: Replace MO_TE by mo_endian (Zalasr extension) Philippe Mathieu-Daudé
@ 2026-03-18 10:31 ` Philippe Mathieu-Daudé
2026-03-26 2:21 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 15/16] target/riscv: Use MO_LE for instruction fetch Philippe Mathieu-Daudé
` (2 subsequent siblings)
16 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-03-18 10:31 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell,
Philippe Mathieu-Daudé, Alistair Francis, Liu Zhiwei,
Djordje Todorovic
We only build the RISC-V target using little endianness order,
therefore the MO_TE definitions expand to the little endian
one. Use the latter which is more explicit.
Mechanical change running:
$ sed -i -e s/MO_TE/MO_LE/ \
$(git grep -wl MO_TE target/riscv/)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/internals.h | 2 +-
target/riscv/translate.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 860c47732b6..460346dd6de 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -71,7 +71,7 @@ static inline MemOp mo_endian_env(CPURISCVState *env)
* - MSTATUS_MBE (Machine-mode)
* but we don't implement that yet.
*/
- return MO_TE;
+ return MO_LE;
}
/* share data between vector helpers and decode code */
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index cb4f4436018..6f8b8e9d19a 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -135,7 +135,7 @@ static inline MemOp mo_endian(DisasContext *ctx)
* - MSTATUS_MBE (Machine-mode)
* but we don't implement that yet.
*/
- return MO_TE;
+ return MO_LE;
}
#ifdef TARGET_RISCV32
--
2.53.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH-for-11.1 15/16] target/riscv: Use MO_LE for instruction fetch
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2026-03-18 10:31 ` [PATCH-for-11.1 14/16] target/riscv: Replace MO_TE -> MO_LE Philippe Mathieu-Daudé
@ 2026-03-18 10:31 ` Philippe Mathieu-Daudé
2026-03-20 11:27 ` Djordje Todorovic
2026-03-18 10:31 ` [PATCH-for-11.1 16/16] configs/targets: Forbid RISC-V to use legacy native endianness APIs Philippe Mathieu-Daudé
2026-03-26 2:28 ` [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Alistair Francis
16 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-03-18 10:31 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell,
Philippe Mathieu-Daudé, Alistair Francis, Liu Zhiwei,
Djordje Todorovic
From: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>
RISC-V instructions are always little-endian regardless of the data
endianness mode configured via mstatus SBE/MBE/UBE bits.
Currently, instruction fetches in decode_opc() and the page boundary
check use mo_endian(ctx), which returns MO_TE. This happens to work
today because RISC-V targets are little-endian only, but is
semantically incorrect and will break once mo_endian() is updated to
respect runtime data endianness for big-endian support.
Use MO_LE explicitly for all instruction fetch paths. Data memory
operations (AMOs, loads/stores via mxl_memop) continue to use
mo_endian(ctx) as they should respect the configured data endianness.
Not-Signed-off-by: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20260311115910.564481-3-djordje.todorovic@htecgroup.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6f8b8e9d19a..5df5b738495 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1255,7 +1255,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
* additional page fault.
*/
opcode = translator_ldl_end(env, &ctx->base, ctx->base.pc_next,
- mo_endian(ctx));
+ MO_LE);
} else {
/*
* For unaligned pc, instruction preload may trigger additional
@@ -1263,7 +1263,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
*/
opcode = (uint32_t) translator_lduw_end(env, &ctx->base,
ctx->base.pc_next,
- mo_endian(ctx));
+ MO_LE);
}
ctx->ol = ctx->xl;
@@ -1285,7 +1285,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
opcode = deposit32(opcode, 16, 16,
translator_lduw_end(env, &ctx->base,
ctx->base.pc_next + 2,
- mo_endian(ctx)));
+ MO_LE));
}
ctx->opcode = opcode;
@@ -1401,7 +1401,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) {
uint16_t next_insn =
translator_lduw_end(env, &ctx->base, ctx->base.pc_next,
- mo_endian(ctx));
+ MO_LE);
int len = insn_len(next_insn);
if (!translator_is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) {
--
2.53.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH-for-11.1 16/16] configs/targets: Forbid RISC-V to use legacy native endianness APIs
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2026-03-18 10:31 ` [PATCH-for-11.1 15/16] target/riscv: Use MO_LE for instruction fetch Philippe Mathieu-Daudé
@ 2026-03-18 10:31 ` Philippe Mathieu-Daudé
2026-03-26 2:21 ` Alistair Francis
2026-03-26 2:28 ` [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Alistair Francis
16 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-03-18 10:31 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell,
Philippe Mathieu-Daudé, Alistair Francis, Liu Zhiwei,
Djordje Todorovic, Laurent Vivier, Kyle Evans
All RISC-V related binaries are buildable without a single
use of the legacy "native endian" API. Set the transitional
TARGET_USE_LEGACY_NATIVE_ENDIAN_API definition to forbid
further uses of the legacy API.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
configs/targets/riscv32-linux-user.mak | 1 +
configs/targets/riscv32-softmmu.mak | 1 +
configs/targets/riscv64-bsd-user.mak | 1 +
configs/targets/riscv64-linux-user.mak | 1 +
configs/targets/riscv64-softmmu.mak | 1 +
5 files changed, 5 insertions(+)
diff --git a/configs/targets/riscv32-linux-user.mak b/configs/targets/riscv32-linux-user.mak
index f069ab9a0f9..d88fdf5e1b2 100644
--- a/configs/targets/riscv32-linux-user.mak
+++ b/configs/targets/riscv32-linux-user.mak
@@ -8,3 +8,4 @@ TARGET_SYSTBL_ABI=32
TARGET_SYSTBL_ABI=common,32,riscv,memfd_secret
TARGET_SYSTBL=syscall.tbl
TARGET_LONG_BITS=32
+TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-softmmu.mak
index 26080599be7..5d5016d0083 100644
--- a/configs/targets/riscv32-softmmu.mak
+++ b/configs/targets/riscv32-softmmu.mak
@@ -5,3 +5,4 @@ TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml ri
TARGET_NEED_FDT=y
TARGET_LONG_BITS=32
TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
+TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
diff --git a/configs/targets/riscv64-bsd-user.mak b/configs/targets/riscv64-bsd-user.mak
index bc85d9ed04e..5b4e138099f 100644
--- a/configs/targets/riscv64-bsd-user.mak
+++ b/configs/targets/riscv64-bsd-user.mak
@@ -3,3 +3,4 @@ TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml
TARGET_LONG_BITS=64
+TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
diff --git a/configs/targets/riscv64-linux-user.mak b/configs/targets/riscv64-linux-user.mak
index bca08645124..35621520c56 100644
--- a/configs/targets/riscv64-linux-user.mak
+++ b/configs/targets/riscv64-linux-user.mak
@@ -8,3 +8,4 @@ TARGET_SYSTBL_ABI=64
TARGET_SYSTBL_ABI=common,64,riscv,rlimit,memfd_secret
TARGET_SYSTBL=syscall.tbl
TARGET_LONG_BITS=64
+TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-softmmu.mak
index 5059c550480..a10dc03c04c 100644
--- a/configs/targets/riscv64-softmmu.mak
+++ b/configs/targets/riscv64-softmmu.mak
@@ -6,3 +6,4 @@ TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml ri
TARGET_NEED_FDT=y
TARGET_LONG_BITS=64
TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
+TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
--
2.53.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH-for-11.1 01/16] hw/riscv: Mark RISC-V specific peripherals as little-endian
2026-03-18 10:31 ` [PATCH-for-11.1 01/16] hw/riscv: Mark RISC-V specific peripherals as little-endian Philippe Mathieu-Daudé
@ 2026-03-19 1:43 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2026-03-19 1:43 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell, Liu Zhiwei,
Djordje Todorovic, Marc-André Lureau, Paolo Bonzini,
Edgar E. Iglesias, qemu-arm
On Wed, Mar 18, 2026 at 8:34 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> These devices are only used by the RISC-V targets, which are
> only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN
> definition expand to DEVICE_LITTLE_ENDIAN (besides, the
> DEVICE_BIG_ENDIAN case isn't tested). Simplify directly
> using DEVICE_LITTLE_ENDIAN.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/char/ibex_uart.c | 2 +-
> hw/char/shakti_uart.c | 2 +-
> hw/char/sifive_uart.c | 2 +-
> hw/misc/sifive_e_aon.c | 2 +-
> hw/misc/sifive_e_prci.c | 2 +-
> hw/misc/sifive_u_otp.c | 2 +-
> hw/misc/sifive_u_prci.c | 2 +-
> hw/riscv/riscv-iommu.c | 2 +-
> hw/sd/cadence_sdhci.c | 2 +-
> hw/timer/ibex_timer.c | 2 +-
> hw/timer/sifive_pwm.c | 2 +-
> 11 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
> index 127d219df3c..26ed1aea140 100644
> --- a/hw/char/ibex_uart.c
> +++ b/hw/char/ibex_uart.c
> @@ -470,7 +470,7 @@ static void fifo_trigger_update(void *opaque)
> static const MemoryRegionOps ibex_uart_ops = {
> .read = ibex_uart_read,
> .write = ibex_uart_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> .impl.min_access_size = 4,
> .impl.max_access_size = 4,
> };
> diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c
> index 2d1bc9cb8e2..d38920a03a0 100644
> --- a/hw/char/shakti_uart.c
> +++ b/hw/char/shakti_uart.c
> @@ -103,7 +103,7 @@ static void shakti_uart_write(void *opaque, hwaddr addr,
> static const MemoryRegionOps shakti_uart_ops = {
> .read = shakti_uart_read,
> .write = shakti_uart_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> .impl = {.min_access_size = 1, .max_access_size = 4},
> .valid = {.min_access_size = 1, .max_access_size = 4},
> };
> diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
> index af17cf9a6ce..4e31842df5c 100644
> --- a/hw/char/sifive_uart.c
> +++ b/hw/char/sifive_uart.c
> @@ -206,7 +206,7 @@ static void fifo_trigger_update(void *opaque)
> static const MemoryRegionOps sifive_uart_ops = {
> .read = sifive_uart_read,
> .write = sifive_uart_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> .valid = {
> .min_access_size = 4,
> .max_access_size = 4
> diff --git a/hw/misc/sifive_e_aon.c b/hw/misc/sifive_e_aon.c
> index e78f4f56725..ff2a7c18235 100644
> --- a/hw/misc/sifive_e_aon.c
> +++ b/hw/misc/sifive_e_aon.c
> @@ -250,7 +250,7 @@ sifive_e_aon_write(void *opaque, hwaddr addr,
> static const MemoryRegionOps sifive_e_aon_ops = {
> .read = sifive_e_aon_read,
> .write = sifive_e_aon_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> .impl = {
> .min_access_size = 4,
> .max_access_size = 4
> diff --git a/hw/misc/sifive_e_prci.c b/hw/misc/sifive_e_prci.c
> index 400664aabae..a4a60e7b406 100644
> --- a/hw/misc/sifive_e_prci.c
> +++ b/hw/misc/sifive_e_prci.c
> @@ -75,7 +75,7 @@ static void sifive_e_prci_write(void *opaque, hwaddr addr,
> static const MemoryRegionOps sifive_e_prci_ops = {
> .read = sifive_e_prci_read,
> .write = sifive_e_prci_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> .valid = {
> .min_access_size = 4,
> .max_access_size = 4
> diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
> index 7205374bc39..cececd4f7a8 100644
> --- a/hw/misc/sifive_u_otp.c
> +++ b/hw/misc/sifive_u_otp.c
> @@ -187,7 +187,7 @@ static void sifive_u_otp_write(void *opaque, hwaddr addr,
> static const MemoryRegionOps sifive_u_otp_ops = {
> .read = sifive_u_otp_read,
> .write = sifive_u_otp_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> .valid = {
> .min_access_size = 4,
> .max_access_size = 4
> diff --git a/hw/misc/sifive_u_prci.c b/hw/misc/sifive_u_prci.c
> index f51588623ab..4674d5925ea 100644
> --- a/hw/misc/sifive_u_prci.c
> +++ b/hw/misc/sifive_u_prci.c
> @@ -112,7 +112,7 @@ static void sifive_u_prci_write(void *opaque, hwaddr addr,
> static const MemoryRegionOps sifive_u_prci_ops = {
> .read = sifive_u_prci_read,
> .write = sifive_u_prci_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> .valid = {
> .min_access_size = 4,
> .max_access_size = 4
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index 98345b1280b..ef5d7df2385 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -2375,7 +2375,7 @@ static MemTxResult riscv_iommu_mmio_read(void *opaque, hwaddr addr,
> static const MemoryRegionOps riscv_iommu_mmio_ops = {
> .read_with_attrs = riscv_iommu_mmio_read,
> .write_with_attrs = riscv_iommu_mmio_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> .impl = {
> .min_access_size = 4,
> .max_access_size = 8,
> diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c
> index d576855a1a8..8476baf67fb 100644
> --- a/hw/sd/cadence_sdhci.c
> +++ b/hw/sd/cadence_sdhci.c
> @@ -122,7 +122,7 @@ static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
> static const MemoryRegionOps cadence_sdhci_ops = {
> .read = cadence_sdhci_read,
> .write = cadence_sdhci_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> .impl = {
> .min_access_size = 4,
> .max_access_size = 4,
> diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
> index ee186521893..0f12531934d 100644
> --- a/hw/timer/ibex_timer.c
> +++ b/hw/timer/ibex_timer.c
> @@ -234,7 +234,7 @@ static void ibex_timer_write(void *opaque, hwaddr addr,
> static const MemoryRegionOps ibex_timer_ops = {
> .read = ibex_timer_read,
> .write = ibex_timer_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> .impl.min_access_size = 4,
> .impl.max_access_size = 4,
> };
> diff --git a/hw/timer/sifive_pwm.c b/hw/timer/sifive_pwm.c
> index 780eaa50799..4f4f566cd4b 100644
> --- a/hw/timer/sifive_pwm.c
> +++ b/hw/timer/sifive_pwm.c
> @@ -388,7 +388,7 @@ static void sifive_pwm_reset(DeviceState *dev)
> static const MemoryRegionOps sifive_pwm_ops = {
> .read = sifive_pwm_read,
> .write = sifive_pwm_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> };
>
> static const VMStateDescription vmstate_sifive_pwm = {
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH-for-11.1 02/16] target/riscv: Use explicit little-endian LD/ST API
2026-03-18 10:31 ` [PATCH-for-11.1 02/16] target/riscv: Use explicit little-endian LD/ST API Philippe Mathieu-Daudé
@ 2026-03-19 3:09 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2026-03-19 3:09 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell, Liu Zhiwei,
Djordje Todorovic
On Wed, Mar 18, 2026 at 8:33 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> We only build our RISC-V targets as little-endian, therefore
> the LD/ST API expands to its little-endian variant. Directly
> use the latter.
>
> Mechanical change running:
>
> $ for a in uw w l q; do \
> sed -i -e "s/ld${a}_p(/ld${a}_le_p(/" \
> $(git grep -wlE '(ld|st)u?[wlq]_p' target/riscv);
> done
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index dd6c861a90e..c28832e0e39 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1365,9 +1365,9 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> }
>
> if (riscv_cpu_mxl(env) == MXL_RV32) {
> - pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
> + pte = address_space_ldl_le(cs->as, pte_addr, attrs, &res);
> } else {
> - pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
> + pte = address_space_ldq_le(cs->as, pte_addr, attrs, &res);
> }
>
> if (res != MEMTX_OK) {
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH-for-11.1 15/16] target/riscv: Use MO_LE for instruction fetch
2026-03-18 10:31 ` [PATCH-for-11.1 15/16] target/riscv: Use MO_LE for instruction fetch Philippe Mathieu-Daudé
@ 2026-03-20 11:27 ` Djordje Todorovic
0 siblings, 0 replies; 34+ messages in thread
From: Djordje Todorovic @ 2026-03-20 11:27 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel@nongnu.org
Cc: Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv@nongnu.org, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell, Liu Zhiwei
On 3/18/26 11:31, Philippe Mathieu-Daudé wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> From: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>
>
> RISC-V instructions are always little-endian regardless of the data
> endianness mode configured via mstatus SBE/MBE/UBE bits.
>
> Currently, instruction fetches in decode_opc() and the page boundary
> check use mo_endian(ctx), which returns MO_TE. This happens to work
> today because RISC-V targets are little-endian only, but is
> semantically incorrect and will break once mo_endian() is updated to
> respect runtime data endianness for big-endian support.
>
> Use MO_LE explicitly for all instruction fetch paths. Data memory
> operations (AMOs, loads/stores via mxl_memop) continue to use
> mo_endian(ctx) as they should respect the configured data endianness.
>
> Not-Signed-off-by: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Message-ID: <20260311115910.564481-3-djordje.todorovic@htecgroup.com>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/riscv/translate.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 6f8b8e9d19a..5df5b738495 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1255,7 +1255,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
> * additional page fault.
> */
> opcode = translator_ldl_end(env, &ctx->base, ctx->base.pc_next,
> - mo_endian(ctx));
> + MO_LE);
> } else {
> /*
> * For unaligned pc, instruction preload may trigger additional
> @@ -1263,7 +1263,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
> */
> opcode = (uint32_t) translator_lduw_end(env, &ctx->base,
> ctx->base.pc_next,
> - mo_endian(ctx));
> + MO_LE);
> }
> ctx->ol = ctx->xl;
>
> @@ -1285,7 +1285,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
> opcode = deposit32(opcode, 16, 16,
> translator_lduw_end(env, &ctx->base,
> ctx->base.pc_next + 2,
> - mo_endian(ctx)));
> + MO_LE));
> }
> ctx->opcode = opcode;
>
> @@ -1401,7 +1401,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
> if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) {
> uint16_t next_insn =
> translator_lduw_end(env, &ctx->base, ctx->base.pc_next,
> - mo_endian(ctx));
> + MO_LE);
> int len = insn_len(next_insn);
>
> if (!translator_is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) {
> --
> 2.53.0
>
Signed-off-by: Djordje Todorovic<Djordje.Todorovic@htecgroup.com>
Thank you!
I will rebase the Big-Endian changes on top of this patch-set.
Best,
Djordje
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH-for-11.1 03/16] target/riscv: Make LQ and SQ use 128-bit ld/st
2026-03-18 10:31 ` [PATCH-for-11.1 03/16] target/riscv: Make LQ and SQ use 128-bit ld/st Philippe Mathieu-Daudé
@ 2026-03-26 2:06 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2026-03-26 2:06 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell, Liu Zhiwei,
Djordje Todorovic, Richard Henderson
On Wed, Mar 18, 2026 at 8:34 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
>
> The lq and sq helpers for the experimental rv128 architecture
> currently use direct memory accesses.
> Replace these direct accesses with the standard
> tcg_gen_qemu_{ld,st}_i128 TCG helpers that handle endianness
> issues.
>
> Reported-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Message-ID: <20260101181442.2489496-2-frederic.petrot@univ-grenoble-alpes.fr>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 32 ++++++++++++++++++-------
> 1 file changed, 24 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index 54b9b4f2413..2c82ae41a77 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -377,6 +377,9 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
> TCGv destl = dest_gpr(ctx, a->rd);
> TCGv desth = dest_gprh(ctx, a->rd);
> TCGv addrl = tcg_temp_new();
> + TCGv_i128 t16 = tcg_temp_new_i128();
> + TCGv_i64 tl = tcg_temp_new_i64();
> + TCGv_i64 th = tcg_temp_new_i64();
>
> tcg_gen_addi_tl(addrl, src1l, a->imm);
>
> @@ -388,10 +391,14 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
> tcg_gen_movi_tl(desth, 0);
> }
> } else {
> - /* assume little-endian memory access for now */
> - tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, MO_TEUQ);
> - tcg_gen_addi_tl(addrl, addrl, 8);
> - tcg_gen_qemu_ld_tl(desth, addrl, ctx->mem_idx, MO_TEUQ);
> + tcg_gen_qemu_ld_i128(t16, addrl, ctx->mem_idx, memop);
> + if (mo_endian(ctx) == MO_LE) {
> + tcg_gen_extr_i128_i64(tl, th, t16);
> + } else {
> + tcg_gen_extr_i128_i64(th, tl, t16);
> + }
> + tcg_gen_trunc_i64_tl(destl, tl);
> + tcg_gen_trunc_i64_tl(desth, th);
> }
>
> gen_set_gpr128(ctx, a->rd, destl, desth);
> @@ -488,16 +495,25 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)
> TCGv src2l = get_gpr(ctx, a->rs2, EXT_NONE);
> TCGv src2h = get_gprh(ctx, a->rs2);
> TCGv addrl = tcg_temp_new();
> + TCGv_i128 t16 = tcg_temp_new_i128();
> + TCGv_i64 tl = tcg_temp_new_i64();
> + TCGv_i64 th = tcg_temp_new_i64();
>
> tcg_gen_addi_tl(addrl, src1l, a->imm);
>
> if ((memop & MO_SIZE) <= MO_64) {
> tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop);
> } else {
> - /* little-endian memory access assumed for now */
> - tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, MO_TEUQ);
> - tcg_gen_addi_tl(addrl, addrl, 8);
> - tcg_gen_qemu_st_tl(src2h, addrl, ctx->mem_idx, MO_TEUQ);
> +
> + tcg_gen_ext_tl_i64(tl, src2l);
> + tcg_gen_ext_tl_i64(th, src2h);
> +
> + if (mo_endian(ctx) == MO_LE) {
> + tcg_gen_concat_i64_i128(t16, tl, th);
> + } else {
> + tcg_gen_concat_i64_i128(t16, th, tl);
> + }
> + tcg_gen_qemu_st_i128(t16, addrl, ctx->mem_idx, memop);
> }
> return true;
> }
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH-for-11.1 04/16] target/riscv: Remove MTTCG check for x-rv128 CPU model
2026-03-18 10:31 ` [PATCH-for-11.1 04/16] target/riscv: Remove MTTCG check for x-rv128 CPU model Philippe Mathieu-Daudé
@ 2026-03-26 2:06 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2026-03-26 2:06 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell, Liu Zhiwei,
Djordje Todorovic
On Wed, Mar 18, 2026 at 8:33 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
>
> We had to check that mttcg was not used when executing QEMU with
> -cpu x-rv128 as a single 128-bit access was done as two distinct
> 64-bit accesses.
> Now that we use the 128-bit ld/st that access the data atomically,
> this check is no longer necessary.
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Message-ID: <20260101181442.2489496-3-frederic.petrot@univ-grenoble-alpes.fr>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 10 ----------
> 1 file changed, 10 deletions(-)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 988b2d905f5..3407191c224 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -1305,16 +1305,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
> }
>
> #ifndef CONFIG_USER_ONLY
> - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
> -
> - if (mcc->def->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
> - /* Missing 128-bit aligned atomics */
> - error_setg(errp,
> - "128-bit RISC-V currently does not work with Multi "
> - "Threaded TCG. Please use: -accel tcg,thread=single");
> - return false;
> - }
> -
> CPURISCVState *env = &cpu->env;
>
> tcg_cflags_set(CPU(cs), CF_PCREL);
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH-for-11.1 05/16] target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again)
2026-03-18 10:31 ` [PATCH-for-11.1 05/16] target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again) Philippe Mathieu-Daudé
@ 2026-03-26 2:07 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2026-03-26 2:07 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell, Liu Zhiwei,
Djordje Todorovic
On Wed, Mar 18, 2026 at 8:33 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Following commit 73ae67fd4e6, extract the implicit MO_TE
> definition in order to replace it.
>
> Mechanical change using:
>
> $ for n in UW UL UQ UO SW SL SQ; do \
> sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
> $(git grep -l MO_TE$n target/riscv); \
> done
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvzalasr.c.inc | 12 ++++++------
> target/riscv/insn_trans/trans_xmips.c.inc | 16 ++++++++--------
> target/riscv/insn_trans/trans_zilsd.c.inc | 4 ++--
> 3 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/insn_trans/trans_rvzalasr.c.inc
> index bf86805cef6..525f01ca347 100644
> --- a/target/riscv/insn_trans/trans_rvzalasr.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc
> @@ -49,20 +49,20 @@ static bool trans_lb_aqrl(DisasContext *ctx, arg_lb_aqrl *a)
> static bool trans_lh_aqrl(DisasContext *ctx, arg_lh_aqrl *a)
> {
> REQUIRE_ZALASR(ctx);
> - return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESW));
> + return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
> }
>
> static bool trans_lw_aqrl(DisasContext *ctx, arg_lw_aqrl *a)
> {
> REQUIRE_ZALASR(ctx);
> - return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESL));
> + return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
> }
>
> static bool trans_ld_aqrl(DisasContext *ctx, arg_ld_aqrl *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_ZALASR(ctx);
> - return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TEUQ));
> + return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
> }
>
> static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
> @@ -96,18 +96,18 @@ static bool trans_sb_aqrl(DisasContext *ctx, arg_sb_aqrl *a)
> static bool trans_sh_aqrl(DisasContext *ctx, arg_sh_aqrl *a)
> {
> REQUIRE_ZALASR(ctx);
> - return gen_store_release(ctx, a, (MO_ALIGN | MO_TESW));
> + return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
> }
>
> static bool trans_sw_aqrl(DisasContext *ctx, arg_sw_aqrl *a)
> {
> REQUIRE_ZALASR(ctx);
> - return gen_store_release(ctx, a, (MO_ALIGN | MO_TESL));
> + return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
> }
>
> static bool trans_sd_aqrl(DisasContext *ctx, arg_sd_aqrl *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_ZALASR(ctx);
> - return gen_store_release(ctx, a, (MO_ALIGN | MO_TEUQ));
> + return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
> }
> diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_trans/trans_xmips.c.inc
> index 9a72f3392f1..37572563ae9 100644
> --- a/target/riscv/insn_trans/trans_xmips.c.inc
> +++ b/target/riscv/insn_trans/trans_xmips.c.inc
> @@ -56,11 +56,11 @@ static bool trans_ldp(DisasContext *ctx, arg_ldp *a)
> TCGv addr = tcg_temp_new();
>
> tcg_gen_addi_tl(addr, src, a->imm_y);
> - tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESQ);
> + tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SQ);
> gen_set_gpr(ctx, a->rd, dest0);
>
> tcg_gen_addi_tl(addr, addr, 8);
> - tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESQ);
> + tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SQ);
> gen_set_gpr(ctx, a->rs3, dest1);
>
> return true;
> @@ -77,11 +77,11 @@ static bool trans_lwp(DisasContext *ctx, arg_lwp *a)
> TCGv addr = tcg_temp_new();
>
> tcg_gen_addi_tl(addr, src, a->imm_x);
> - tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESL);
> + tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SL);
> gen_set_gpr(ctx, a->rd, dest0);
>
> tcg_gen_addi_tl(addr, addr, 4);
> - tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESL);
> + tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SL);
> gen_set_gpr(ctx, a->rs3, dest1);
>
> return true;
> @@ -99,10 +99,10 @@ static bool trans_sdp(DisasContext *ctx, arg_sdp *a)
> TCGv addr = tcg_temp_new();
>
> tcg_gen_addi_tl(addr, src, a->imm_w);
> - tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TEUQ);
> + tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_UQ);
>
> tcg_gen_addi_tl(addr, addr, 8);
> - tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TEUQ);
> + tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_UQ);
>
> return true;
> }
> @@ -118,10 +118,10 @@ static bool trans_swp(DisasContext *ctx, arg_swp *a)
> TCGv addr = tcg_temp_new();
>
> tcg_gen_addi_tl(addr, src, a->imm_v);
> - tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TESL);
> + tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_SL);
>
> tcg_gen_addi_tl(addr, addr, 4);
> - tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TESL);
> + tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_SL);
>
> return true;
> }
> diff --git a/target/riscv/insn_trans/trans_zilsd.c.inc b/target/riscv/insn_trans/trans_zilsd.c.inc
> index 369c33004b6..445406cf015 100644
> --- a/target/riscv/insn_trans/trans_zilsd.c.inc
> +++ b/target/riscv/insn_trans/trans_zilsd.c.inc
> @@ -30,7 +30,7 @@ static bool gen_load_i64(DisasContext *ctx, arg_ld *a)
> TCGv addr = get_address(ctx, a->rs1, a->imm);
> TCGv_i64 tmp = tcg_temp_new_i64();
>
> - tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TESQ);
> + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
>
> if (a->rd == 0) {
> return true;
> @@ -85,7 +85,7 @@ static bool gen_store_i64(DisasContext *ctx, arg_sd *a)
> } else {
> tcg_gen_concat_tl_i64(tmp, data_low, data_high);
> }
> - tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TESQ);
> + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
>
> return true;
> }
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH-for-11.1 06/16] target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / store_release
2026-03-18 10:31 ` [PATCH-for-11.1 06/16] target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / store_release Philippe Mathieu-Daudé
@ 2026-03-26 2:08 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2026-03-26 2:08 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell, Liu Zhiwei,
Djordje Todorovic
On Wed, Mar 18, 2026 at 8:34 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> All callers of gen_load_acquire() and gen_store_release() set both
> the MO_ALIGN|MO_TE flags. Set them once in each callee.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvzalasr.c.inc | 18 ++++++++++--------
> 1 file changed, 10 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/insn_trans/trans_rvzalasr.c.inc
> index 525f01ca347..2b1f73f650b 100644
> --- a/target/riscv/insn_trans/trans_rvzalasr.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc
> @@ -29,6 +29,7 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)
> return false;
> }
>
> + memop |= MO_ALIGN | MO_TE;
> memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
>
> tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
> @@ -43,26 +44,26 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)
> static bool trans_lb_aqrl(DisasContext *ctx, arg_lb_aqrl *a)
> {
> REQUIRE_ZALASR(ctx);
> - return gen_load_acquire(ctx, a, (MO_ALIGN | MO_SB));
> + return gen_load_acquire(ctx, a, MO_SB);
> }
>
> static bool trans_lh_aqrl(DisasContext *ctx, arg_lh_aqrl *a)
> {
> REQUIRE_ZALASR(ctx);
> - return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
> + return gen_load_acquire(ctx, a, MO_SW);
> }
>
> static bool trans_lw_aqrl(DisasContext *ctx, arg_lw_aqrl *a)
> {
> REQUIRE_ZALASR(ctx);
> - return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
> + return gen_load_acquire(ctx, a, MO_SL);
> }
>
> static bool trans_ld_aqrl(DisasContext *ctx, arg_ld_aqrl *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_ZALASR(ctx);
> - return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
> + return gen_load_acquire(ctx, a, MO_UQ);
> }
>
> static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
> @@ -78,6 +79,7 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
> return false;
> }
>
> + memop |= MO_ALIGN | MO_TE;
> memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
>
> /* Add a memory barrier implied by RL (mandatory) and AQ (optional) */
> @@ -90,24 +92,24 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
> static bool trans_sb_aqrl(DisasContext *ctx, arg_sb_aqrl *a)
> {
> REQUIRE_ZALASR(ctx);
> - return gen_store_release(ctx, a, (MO_ALIGN | MO_SB));
> + return gen_store_release(ctx, a, MO_SB);
> }
>
> static bool trans_sh_aqrl(DisasContext *ctx, arg_sh_aqrl *a)
> {
> REQUIRE_ZALASR(ctx);
> - return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
> + return gen_store_release(ctx, a, MO_SW);
> }
>
> static bool trans_sw_aqrl(DisasContext *ctx, arg_sw_aqrl *a)
> {
> REQUIRE_ZALASR(ctx);
> - return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
> + return gen_store_release(ctx, a, MO_SL);
> }
>
> static bool trans_sd_aqrl(DisasContext *ctx, arg_sd_aqrl *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_ZALASR(ctx);
> - return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
> + return gen_store_release(ctx, a, MO_UQ);
> }
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH-for-11.1 07/16] target/riscv: Factor tiny ldn() helper in gdbstub
2026-03-18 10:31 ` [PATCH-for-11.1 07/16] target/riscv: Factor tiny ldn() helper in gdbstub Philippe Mathieu-Daudé
@ 2026-03-26 2:09 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2026-03-26 2:09 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell, Liu Zhiwei,
Djordje Todorovic
On Wed, Mar 18, 2026 at 8:33 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> In preparation of having this helper handle CPU runtime
> endianness changes, factor the ldn() helper out.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/gdbstub.c | 22 +++++++++++++---------
> 1 file changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 6a5b7a82fd4..be42566bcc8 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -47,6 +47,11 @@ static const struct TypeSize vec_lanes[] = {
> { "uint8", "bytes", 8, 'b' },
> };
>
> +static uint64_t ldn(CPURISCVState *env, uint8_t *mem_buf, size_t regsz)
> +{
> + return ldn_p(mem_buf, regsz);
> +}
> +
> int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
> {
> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
> @@ -84,15 +89,15 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
>
> switch (mcc->def->misa_mxl_max) {
> case MXL_RV32:
> - tmp = (int32_t)ldl_p(mem_buf);
> + tmp = (int32_t)ldn(env, mem_buf, 4);
> length = 4;
> break;
> case MXL_RV64:
> case MXL_RV128:
> if (env->xl < MXL_RV64) {
> - tmp = (int32_t)ldq_p(mem_buf);
> + tmp = (int32_t)ldn(env, mem_buf, 8);
> } else {
> - tmp = ldq_p(mem_buf);
> + tmp = ldn(env, mem_buf, 8);
> }
> length = 8;
> break;
> @@ -130,7 +135,7 @@ static int riscv_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n)
> CPURISCVState *env = &cpu->env;
>
> if (n < 32) {
> - env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
> + env->fpr[n] = ldn(env, mem_buf, 8); /* always 64-bit */
> return sizeof(uint64_t);
> }
> return 0;
> @@ -162,7 +167,7 @@ static int riscv_gdb_set_vector(CPUState *cs, uint8_t *mem_buf, int n)
> if (n < 32) {
> int i;
> for (i = 0; i < vlenb; i += 8) {
> - env->vreg[(n * vlenb + i) / 8] = ldq_p(mem_buf + i);
> + env->vreg[(n * vlenb + i) / 8] = ldn(env, mem_buf + i, 8);
> }
> return vlenb;
> }
> @@ -194,7 +199,7 @@ static int riscv_gdb_set_csr(CPUState *cs, uint8_t *mem_buf, int n)
> const unsigned regsz = riscv_cpu_is_32bit(cpu) ? 4 : 8;
>
> if (n < CSR_TABLE_SIZE) {
> - uint64_t val = ldn_p(mem_buf, regsz);
> + uint64_t val = ldn(env, mem_buf, regsz);
> int result;
>
> result = riscv_csrrw_debug(env, n, NULL, val, -1);
> @@ -230,8 +235,7 @@ static int riscv_gdb_set_virtual(CPUState *cs, uint8_t *mem_buf, int n)
> const unsigned regsz = riscv_cpu_is_32bit(cpu) ? 4 : 8;
> #ifndef CONFIG_USER_ONLY
> CPURISCVState *env = &cpu->env;
> -
> - target_ulong new_priv = ldn_p(mem_buf, regsz) & 0x3;
> + uint64_t new_priv = ldn(env, mem_buf, regsz) & 0x3;
> bool new_virt = 0;
>
> if (new_priv == PRV_RESERVED) {
> @@ -239,7 +243,7 @@ static int riscv_gdb_set_virtual(CPUState *cs, uint8_t *mem_buf, int n)
> }
>
> if (new_priv != PRV_M) {
> - new_virt = (ldn_p(mem_buf, regsz) & BIT(2)) >> 2;
> + new_virt = (ldn(env, mem_buf, regsz) & BIT(2)) >> 2;
> }
>
> if (riscv_has_ext(env, RVH) && new_virt != env->virt_enabled) {
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH-for-11.1 08/16] target/riscv: Simplify riscv_cpu_gdb_write_register()
2026-03-18 10:31 ` [PATCH-for-11.1 08/16] target/riscv: Simplify riscv_cpu_gdb_write_register() Philippe Mathieu-Daudé
@ 2026-03-26 2:12 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2026-03-26 2:12 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell, Liu Zhiwei,
Djordje Todorovic
On Wed, Mar 18, 2026 at 8:34 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Use a single ldn() call, sign-extend once.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> Note I'm skeptical about 128-bit registers path, but this
> would be a pre-existing issue.
> ---
> target/riscv/gdbstub.c | 25 ++++++-------------------
> 1 file changed, 6 insertions(+), 19 deletions(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index be42566bcc8..a5c12638782 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -84,33 +84,20 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> - int length = 0;
> - uint64_t tmp;
> + const size_t regsize = mcc->def->misa_mxl_max == MXL_RV32 ? 4 : 8;
> + uint64_t tmp = ldn(env, mem_buf, regsize);
>
> - switch (mcc->def->misa_mxl_max) {
> - case MXL_RV32:
> - tmp = (int32_t)ldn(env, mem_buf, 4);
> - length = 4;
> - break;
> - case MXL_RV64:
> - case MXL_RV128:
> - if (env->xl < MXL_RV64) {
> - tmp = (int32_t)ldn(env, mem_buf, 8);
> - } else {
> - tmp = ldn(env, mem_buf, 8);
> - }
> - length = 8;
> - break;
> - default:
> - g_assert_not_reached();
> + if (env->xl < MXL_RV64) {
> + tmp = (int32_t)tmp;
> }
> +
> if (n > 0 && n < 32) {
> env->gpr[n] = tmp;
> } else if (n == 32) {
> env->pc = tmp;
> }
>
> - return length;
> + return regsize;
> }
>
> static int riscv_gdb_get_fpu(CPUState *cs, GByteArray *buf, int n)
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH-for-11.1 09/16] target/riscv: Expose mo_endian_env()
2026-03-18 10:31 ` [PATCH-for-11.1 09/16] target/riscv: Expose mo_endian_env() Philippe Mathieu-Daudé
@ 2026-03-26 2:13 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2026-03-26 2:13 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell, Liu Zhiwei,
Djordje Todorovic
On Wed, Mar 18, 2026 at 8:34 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Move mo_endian_env() definition to "internals.h" for re-use.
> Do not restrict to system emulation only because this will
> also be used by user emulation code.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/internals.h | 12 ++++++++++++
> target/riscv/op_helper.c | 14 --------------
> 2 files changed, 12 insertions(+), 14 deletions(-)
>
> diff --git a/target/riscv/internals.h b/target/riscv/internals.h
> index 35b923c4bf5..860c47732b6 100644
> --- a/target/riscv/internals.h
> +++ b/target/riscv/internals.h
> @@ -62,6 +62,18 @@ static inline bool mmuidx_2stage(int mmu_idx)
> return mmu_idx & MMU_2STAGE_BIT;
> }
>
> +static inline MemOp mo_endian_env(CPURISCVState *env)
> +{
> + /*
> + * A couple of bits in MSTATUS set the endianness:
> + * - MSTATUS_UBE (User-mode),
> + * - MSTATUS_SBE (Supervisor-mode),
> + * - MSTATUS_MBE (Machine-mode)
> + * but we don't implement that yet.
> + */
> + return MO_TE;
> +}
> +
> /* share data between vector helpers and decode code */
> FIELD(VDATA, VM, 0, 1)
> FIELD(VDATA, LMUL, 1, 3)
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 6ccc127c304..dde40a55493 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -28,20 +28,6 @@
> #include "exec/tlb-flags.h"
> #include "trace.h"
>
> -#ifndef CONFIG_USER_ONLY
> -static inline MemOp mo_endian_env(CPURISCVState *env)
> -{
> - /*
> - * A couple of bits in MSTATUS set the endianness:
> - * - MSTATUS_UBE (User-mode),
> - * - MSTATUS_SBE (Supervisor-mode),
> - * - MSTATUS_MBE (Machine-mode)
> - * but we don't implement that yet.
> - */
> - return MO_TE;
> -}
> -#endif
> -
> /* Exceptions processing helpers */
> G_NORETURN void riscv_raise_exception(CPURISCVState *env,
> RISCVException exception,
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH-for-11.1 10/16] target/riscv: Have gdbstub consider CPU endianness
2026-03-18 10:31 ` [PATCH-for-11.1 10/16] target/riscv: Have gdbstub consider CPU endianness Philippe Mathieu-Daudé
@ 2026-03-26 2:15 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2026-03-26 2:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell, Liu Zhiwei,
Djordje Todorovic
On Wed, Mar 18, 2026 at 8:34 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Consider CPU endianness when accessing registers.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/gdbstub.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index a5c12638782..2c6ccd4761c 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -20,6 +20,7 @@
> #include "exec/gdbstub.h"
> #include "gdbstub/helpers.h"
> #include "cpu.h"
> +#include "internals.h"
>
> struct TypeSize {
> const char *gdb_type;
> @@ -49,7 +50,7 @@ static const struct TypeSize vec_lanes[] = {
>
> static uint64_t ldn(CPURISCVState *env, uint8_t *mem_buf, size_t regsz)
> {
> - return ldn_p(mem_buf, regsz);
> + return (mo_endian_env(env) == MO_LE ? ldn_le_p : ldn_be_p)(mem_buf, regsz);
> }
>
> int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH-for-11.1 11/16] target/riscv: Replace MO_TE by mo_endian (MIPS extension)
2026-03-18 10:31 ` [PATCH-for-11.1 11/16] target/riscv: Replace MO_TE by mo_endian (MIPS extension) Philippe Mathieu-Daudé
@ 2026-03-26 2:17 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2026-03-26 2:17 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell, Liu Zhiwei,
Djordje Todorovic
On Wed, Mar 18, 2026 at 8:34 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Replace compile-time MO_TE evaluation by runtime mo_endian()
> one, which expand target endianness from DisasContext.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_xmips.c.inc | 24 +++++++++++++++--------
> 1 file changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_trans/trans_xmips.c.inc
> index 37572563ae9..c1a30156d36 100644
> --- a/target/riscv/insn_trans/trans_xmips.c.inc
> +++ b/target/riscv/insn_trans/trans_xmips.c.inc
> @@ -47,6 +47,8 @@ static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a)
> /* Load Doubleword Pair. */
> static bool trans_ldp(DisasContext *ctx, arg_ldp *a)
> {
> + MemOp memop = MO_SQ | mo_endian(ctx);
> +
> REQUIRE_XMIPSLSP(ctx);
> REQUIRE_64_OR_128BIT(ctx);
>
> @@ -56,11 +58,11 @@ static bool trans_ldp(DisasContext *ctx, arg_ldp *a)
> TCGv addr = tcg_temp_new();
>
> tcg_gen_addi_tl(addr, src, a->imm_y);
> - tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SQ);
> + tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, memop);
> gen_set_gpr(ctx, a->rd, dest0);
>
> tcg_gen_addi_tl(addr, addr, 8);
> - tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SQ);
> + tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, memop);
> gen_set_gpr(ctx, a->rs3, dest1);
>
> return true;
> @@ -69,6 +71,8 @@ static bool trans_ldp(DisasContext *ctx, arg_ldp *a)
> /* Load Word Pair. */
> static bool trans_lwp(DisasContext *ctx, arg_lwp *a)
> {
> + MemOp memop = MO_SL | mo_endian(ctx);
> +
> REQUIRE_XMIPSLSP(ctx);
>
> TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
> @@ -77,11 +81,11 @@ static bool trans_lwp(DisasContext *ctx, arg_lwp *a)
> TCGv addr = tcg_temp_new();
>
> tcg_gen_addi_tl(addr, src, a->imm_x);
> - tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SL);
> + tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, memop);
> gen_set_gpr(ctx, a->rd, dest0);
>
> tcg_gen_addi_tl(addr, addr, 4);
> - tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SL);
> + tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, memop);
> gen_set_gpr(ctx, a->rs3, dest1);
>
> return true;
> @@ -90,6 +94,8 @@ static bool trans_lwp(DisasContext *ctx, arg_lwp *a)
> /* Store Doubleword Pair. */
> static bool trans_sdp(DisasContext *ctx, arg_sdp *a)
> {
> + MemOp memop = MO_UQ | mo_endian(ctx);
> +
> REQUIRE_XMIPSLSP(ctx);
> REQUIRE_64_OR_128BIT(ctx);
>
> @@ -99,10 +105,10 @@ static bool trans_sdp(DisasContext *ctx, arg_sdp *a)
> TCGv addr = tcg_temp_new();
>
> tcg_gen_addi_tl(addr, src, a->imm_w);
> - tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_UQ);
> + tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, memop);
>
> tcg_gen_addi_tl(addr, addr, 8);
> - tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_UQ);
> + tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, memop);
>
> return true;
> }
> @@ -110,6 +116,8 @@ static bool trans_sdp(DisasContext *ctx, arg_sdp *a)
> /* Store Word Pair. */
> static bool trans_swp(DisasContext *ctx, arg_swp *a)
> {
> + MemOp memop = MO_SL | mo_endian(ctx);
> +
> REQUIRE_XMIPSLSP(ctx);
>
> TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
> @@ -118,10 +126,10 @@ static bool trans_swp(DisasContext *ctx, arg_swp *a)
> TCGv addr = tcg_temp_new();
>
> tcg_gen_addi_tl(addr, src, a->imm_v);
> - tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_SL);
> + tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, memop);
>
> tcg_gen_addi_tl(addr, addr, 4);
> - tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_SL);
> + tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, memop);
>
> return true;
> }
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH-for-11.1 12/16] target/riscv: Replace MO_TE by mo_endian (Zilsd extension)
2026-03-18 10:31 ` [PATCH-for-11.1 12/16] target/riscv: Replace MO_TE by mo_endian (Zilsd extension) Philippe Mathieu-Daudé
@ 2026-03-26 2:18 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2026-03-26 2:18 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell, Liu Zhiwei,
Djordje Todorovic
On Wed, Mar 18, 2026 at 8:34 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Replace compile-time MO_TE evaluation by runtime mo_endian()
> one, which expand target endianness from DisasContext.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_zilsd.c.inc | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_zilsd.c.inc b/target/riscv/insn_trans/trans_zilsd.c.inc
> index 445406cf015..f50c52f22c9 100644
> --- a/target/riscv/insn_trans/trans_zilsd.c.inc
> +++ b/target/riscv/insn_trans/trans_zilsd.c.inc
> @@ -30,7 +30,7 @@ static bool gen_load_i64(DisasContext *ctx, arg_ld *a)
> TCGv addr = get_address(ctx, a->rs1, a->imm);
> TCGv_i64 tmp = tcg_temp_new_i64();
>
> - tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
> + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx));
>
> if (a->rd == 0) {
> return true;
> @@ -85,7 +85,7 @@ static bool gen_store_i64(DisasContext *ctx, arg_sd *a)
> } else {
> tcg_gen_concat_tl_i64(tmp, data_low, data_high);
> }
> - tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
> + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx));
>
> return true;
> }
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH-for-11.1 13/16] target/riscv: Replace MO_TE by mo_endian (Zalasr extension)
2026-03-18 10:31 ` [PATCH-for-11.1 13/16] target/riscv: Replace MO_TE by mo_endian (Zalasr extension) Philippe Mathieu-Daudé
@ 2026-03-26 2:20 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2026-03-26 2:20 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell, Liu Zhiwei,
Djordje Todorovic
On Wed, Mar 18, 2026 at 8:34 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Replace compile-time MO_TE evaluation by runtime mo_endian()
> one, which expand target endianness from DisasContext.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvzalasr.c.inc | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/insn_trans/trans_rvzalasr.c.inc
> index 2b1f73f650b..0f307affecf 100644
> --- a/target/riscv/insn_trans/trans_rvzalasr.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc
> @@ -29,7 +29,7 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)
> return false;
> }
>
> - memop |= MO_ALIGN | MO_TE;
> + memop |= MO_ALIGN | mo_endian(ctx);
> memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
>
> tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
> @@ -79,7 +79,7 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
> return false;
> }
>
> - memop |= MO_ALIGN | MO_TE;
> + memop |= MO_ALIGN | mo_endian(ctx);
> memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
>
> /* Add a memory barrier implied by RL (mandatory) and AQ (optional) */
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH-for-11.1 14/16] target/riscv: Replace MO_TE -> MO_LE
2026-03-18 10:31 ` [PATCH-for-11.1 14/16] target/riscv: Replace MO_TE -> MO_LE Philippe Mathieu-Daudé
@ 2026-03-26 2:21 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2026-03-26 2:21 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell, Liu Zhiwei,
Djordje Todorovic
On Wed, Mar 18, 2026 at 8:34 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> We only build the RISC-V target using little endianness order,
> therefore the MO_TE definitions expand to the little endian
> one. Use the latter which is more explicit.
>
> Mechanical change running:
>
> $ sed -i -e s/MO_TE/MO_LE/ \
> $(git grep -wl MO_TE target/riscv/)
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/internals.h | 2 +-
> target/riscv/translate.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/internals.h b/target/riscv/internals.h
> index 860c47732b6..460346dd6de 100644
> --- a/target/riscv/internals.h
> +++ b/target/riscv/internals.h
> @@ -71,7 +71,7 @@ static inline MemOp mo_endian_env(CPURISCVState *env)
> * - MSTATUS_MBE (Machine-mode)
> * but we don't implement that yet.
> */
> - return MO_TE;
> + return MO_LE;
> }
>
> /* share data between vector helpers and decode code */
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index cb4f4436018..6f8b8e9d19a 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -135,7 +135,7 @@ static inline MemOp mo_endian(DisasContext *ctx)
> * - MSTATUS_MBE (Machine-mode)
> * but we don't implement that yet.
> */
> - return MO_TE;
> + return MO_LE;
> }
>
> #ifdef TARGET_RISCV32
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH-for-11.1 16/16] configs/targets: Forbid RISC-V to use legacy native endianness APIs
2026-03-18 10:31 ` [PATCH-for-11.1 16/16] configs/targets: Forbid RISC-V to use legacy native endianness APIs Philippe Mathieu-Daudé
@ 2026-03-26 2:21 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2026-03-26 2:21 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell, Liu Zhiwei,
Djordje Todorovic, Laurent Vivier, Kyle Evans
On Wed, Mar 18, 2026 at 8:34 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> All RISC-V related binaries are buildable without a single
> use of the legacy "native endian" API. Set the transitional
> TARGET_USE_LEGACY_NATIVE_ENDIAN_API definition to forbid
> further uses of the legacy API.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> configs/targets/riscv32-linux-user.mak | 1 +
> configs/targets/riscv32-softmmu.mak | 1 +
> configs/targets/riscv64-bsd-user.mak | 1 +
> configs/targets/riscv64-linux-user.mak | 1 +
> configs/targets/riscv64-softmmu.mak | 1 +
> 5 files changed, 5 insertions(+)
>
> diff --git a/configs/targets/riscv32-linux-user.mak b/configs/targets/riscv32-linux-user.mak
> index f069ab9a0f9..d88fdf5e1b2 100644
> --- a/configs/targets/riscv32-linux-user.mak
> +++ b/configs/targets/riscv32-linux-user.mak
> @@ -8,3 +8,4 @@ TARGET_SYSTBL_ABI=32
> TARGET_SYSTBL_ABI=common,32,riscv,memfd_secret
> TARGET_SYSTBL=syscall.tbl
> TARGET_LONG_BITS=32
> +TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
> diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-softmmu.mak
> index 26080599be7..5d5016d0083 100644
> --- a/configs/targets/riscv32-softmmu.mak
> +++ b/configs/targets/riscv32-softmmu.mak
> @@ -5,3 +5,4 @@ TARGET_XML_FILES= riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml ri
> TARGET_NEED_FDT=y
> TARGET_LONG_BITS=32
> TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
> +TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
> diff --git a/configs/targets/riscv64-bsd-user.mak b/configs/targets/riscv64-bsd-user.mak
> index bc85d9ed04e..5b4e138099f 100644
> --- a/configs/targets/riscv64-bsd-user.mak
> +++ b/configs/targets/riscv64-bsd-user.mak
> @@ -3,3 +3,4 @@ TARGET_BASE_ARCH=riscv
> TARGET_ABI_DIR=riscv
> TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-virtual.xml
> TARGET_LONG_BITS=64
> +TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
> diff --git a/configs/targets/riscv64-linux-user.mak b/configs/targets/riscv64-linux-user.mak
> index bca08645124..35621520c56 100644
> --- a/configs/targets/riscv64-linux-user.mak
> +++ b/configs/targets/riscv64-linux-user.mak
> @@ -8,3 +8,4 @@ TARGET_SYSTBL_ABI=64
> TARGET_SYSTBL_ABI=common,64,riscv,rlimit,memfd_secret
> TARGET_SYSTBL=syscall.tbl
> TARGET_LONG_BITS=64
> +TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
> diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-softmmu.mak
> index 5059c550480..a10dc03c04c 100644
> --- a/configs/targets/riscv64-softmmu.mak
> +++ b/configs/targets/riscv64-softmmu.mak
> @@ -6,3 +6,4 @@ TARGET_XML_FILES= riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml ri
> TARGET_NEED_FDT=y
> TARGET_LONG_BITS=64
> TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
> +TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2026-03-18 10:31 ` [PATCH-for-11.1 16/16] configs/targets: Forbid RISC-V to use legacy native endianness APIs Philippe Mathieu-Daudé
@ 2026-03-26 2:28 ` Alistair Francis
16 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2026-03-26 2:28 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Weiwei Li, Pierrick Bouvier, Warner Losh,
Frédéric Pétrot, Vijai Kumar K, Anton Johansson,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Jiaxun Yang, Peter Maydell, Liu Zhiwei,
Djordje Todorovic
On Wed, Mar 18, 2026 at 8:33 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Thanks to Frédéric patch on 128-bit registers, we can now
> remove all legacy native endianness API uses of RISC-V.
>
> Djordje: You should (re)base your "Add RISC-V big-endian
> target support" [*] series on this (after addressing the
> review comments) before posting your v4.
>
> [*] https://lore.kernel.org/qemu-devel/20260311115910.564481-1-djordje.todorovic@htecgroup.com/
>
> Djordje Todorovic (1):
> target/riscv: Use MO_LE for instruction fetch
>
> Frédéric Pétrot (2):
> target/riscv: Make LQ and SQ use 128-bit ld/st
> target/riscv: Remove MTTCG check for x-rv128 CPU model
>
> Philippe Mathieu-Daudé (13):
> hw/riscv: Mark RISC-V specific peripherals as little-endian
> target/riscv: Use explicit little-endian LD/ST API
> target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again)
> target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire /
> store_release
> target/riscv: Factor tiny ldn() helper in gdbstub
> target/riscv: Simplify riscv_cpu_gdb_write_register()
> target/riscv: Expose mo_endian_env()
> target/riscv: Have gdbstub consider CPU endianness
> target/riscv: Replace MO_TE by mo_endian (MIPS extension)
> target/riscv: Replace MO_TE by mo_endian (Zilsd extension)
> target/riscv: Replace MO_TE by mo_endian (Zalasr extension)
> target/riscv: Replace MO_TE -> MO_LE
> configs/targets: Forbid RISC-V to use legacy native endianness APIs
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> configs/targets/riscv32-linux-user.mak | 1 +
> configs/targets/riscv32-softmmu.mak | 1 +
> configs/targets/riscv64-bsd-user.mak | 1 +
> configs/targets/riscv64-linux-user.mak | 1 +
> configs/targets/riscv64-softmmu.mak | 1 +
> target/riscv/internals.h | 12 ++++++
> hw/char/ibex_uart.c | 2 +-
> hw/char/shakti_uart.c | 2 +-
> hw/char/sifive_uart.c | 2 +-
> hw/misc/sifive_e_aon.c | 2 +-
> hw/misc/sifive_e_prci.c | 2 +-
> hw/misc/sifive_u_otp.c | 2 +-
> hw/misc/sifive_u_prci.c | 2 +-
> hw/riscv/riscv-iommu.c | 2 +-
> hw/sd/cadence_sdhci.c | 2 +-
> hw/timer/ibex_timer.c | 2 +-
> hw/timer/sifive_pwm.c | 2 +-
> target/riscv/cpu_helper.c | 4 +-
> target/riscv/gdbstub.c | 42 ++++++++------------
> target/riscv/op_helper.c | 14 -------
> target/riscv/tcg/tcg-cpu.c | 10 -----
> target/riscv/translate.c | 10 ++---
> target/riscv/insn_trans/trans_rvi.c.inc | 32 +++++++++++----
> target/riscv/insn_trans/trans_rvzalasr.c.inc | 18 +++++----
> target/riscv/insn_trans/trans_xmips.c.inc | 24 +++++++----
> target/riscv/insn_trans/trans_zilsd.c.inc | 4 +-
> 26 files changed, 104 insertions(+), 93 deletions(-)
>
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2026-03-26 2:29 UTC | newest]
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2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
2026-03-18 10:31 ` [PATCH-for-11.1 01/16] hw/riscv: Mark RISC-V specific peripherals as little-endian Philippe Mathieu-Daudé
2026-03-19 1:43 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 02/16] target/riscv: Use explicit little-endian LD/ST API Philippe Mathieu-Daudé
2026-03-19 3:09 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 03/16] target/riscv: Make LQ and SQ use 128-bit ld/st Philippe Mathieu-Daudé
2026-03-26 2:06 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 04/16] target/riscv: Remove MTTCG check for x-rv128 CPU model Philippe Mathieu-Daudé
2026-03-26 2:06 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 05/16] target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again) Philippe Mathieu-Daudé
2026-03-26 2:07 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 06/16] target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / store_release Philippe Mathieu-Daudé
2026-03-26 2:08 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 07/16] target/riscv: Factor tiny ldn() helper in gdbstub Philippe Mathieu-Daudé
2026-03-26 2:09 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 08/16] target/riscv: Simplify riscv_cpu_gdb_write_register() Philippe Mathieu-Daudé
2026-03-26 2:12 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 09/16] target/riscv: Expose mo_endian_env() Philippe Mathieu-Daudé
2026-03-26 2:13 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 10/16] target/riscv: Have gdbstub consider CPU endianness Philippe Mathieu-Daudé
2026-03-26 2:15 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 11/16] target/riscv: Replace MO_TE by mo_endian (MIPS extension) Philippe Mathieu-Daudé
2026-03-26 2:17 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 12/16] target/riscv: Replace MO_TE by mo_endian (Zilsd extension) Philippe Mathieu-Daudé
2026-03-26 2:18 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 13/16] target/riscv: Replace MO_TE by mo_endian (Zalasr extension) Philippe Mathieu-Daudé
2026-03-26 2:20 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 14/16] target/riscv: Replace MO_TE -> MO_LE Philippe Mathieu-Daudé
2026-03-26 2:21 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 15/16] target/riscv: Use MO_LE for instruction fetch Philippe Mathieu-Daudé
2026-03-20 11:27 ` Djordje Todorovic
2026-03-18 10:31 ` [PATCH-for-11.1 16/16] configs/targets: Forbid RISC-V to use legacy native endianness APIs Philippe Mathieu-Daudé
2026-03-26 2:21 ` Alistair Francis
2026-03-26 2:28 ` [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Alistair Francis
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