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Wed, 25 Mar 2026 19:08:09 -0700 (PDT) MIME-Version: 1.0 References: <20260318103122.97244-1-philmd@linaro.org> <20260318103122.97244-6-philmd@linaro.org> In-Reply-To: <20260318103122.97244-6-philmd@linaro.org> From: Alistair Francis Date: Thu, 26 Mar 2026 12:07:42 +1000 X-Gm-Features: AQROBzABQBPxBf_I3xqf61OlCa8PMjy0dFseMNNiCp9zI3yUlQ9GV9lJbegxzZc Message-ID: Subject: Re: [PATCH-for-11.1 05/16] target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again) To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-devel@nongnu.org, Weiwei Li , Pierrick Bouvier , Warner Losh , =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= , Vijai Kumar K , Anton Johansson , Daniel Henrique Barboza , qemu-riscv@nongnu.org, Alistair Francis , Palmer Dabbelt , Jiaxun Yang , Peter Maydell , Liu Zhiwei , Djordje Todorovic Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=alistair23@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Mar 18, 2026 at 8:33=E2=80=AFPM Philippe Mathieu-Daud=C3=A9 wrote: > > Following commit 73ae67fd4e6, extract the implicit MO_TE > definition in order to replace it. > > Mechanical change using: > > $ for n in UW UL UQ UO SW SL SQ; do \ > sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ > $(git grep -l MO_TE$n target/riscv); \ > done > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn_trans/trans_rvzalasr.c.inc | 12 ++++++------ > target/riscv/insn_trans/trans_xmips.c.inc | 16 ++++++++-------- > target/riscv/insn_trans/trans_zilsd.c.inc | 4 ++-- > 3 files changed, 16 insertions(+), 16 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/= insn_trans/trans_rvzalasr.c.inc > index bf86805cef6..525f01ca347 100644 > --- a/target/riscv/insn_trans/trans_rvzalasr.c.inc > +++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc > @@ -49,20 +49,20 @@ static bool trans_lb_aqrl(DisasContext *ctx, arg_lb_a= qrl *a) > static bool trans_lh_aqrl(DisasContext *ctx, arg_lh_aqrl *a) > { > REQUIRE_ZALASR(ctx); > - return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESW)); > + return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SW)); > } > > static bool trans_lw_aqrl(DisasContext *ctx, arg_lw_aqrl *a) > { > REQUIRE_ZALASR(ctx); > - return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESL)); > + return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SL)); > } > > static bool trans_ld_aqrl(DisasContext *ctx, arg_ld_aqrl *a) > { > REQUIRE_64BIT(ctx); > REQUIRE_ZALASR(ctx); > - return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TEUQ)); > + return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_UQ)); > } > > static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp m= emop) > @@ -96,18 +96,18 @@ static bool trans_sb_aqrl(DisasContext *ctx, arg_sb_a= qrl *a) > static bool trans_sh_aqrl(DisasContext *ctx, arg_sh_aqrl *a) > { > REQUIRE_ZALASR(ctx); > - return gen_store_release(ctx, a, (MO_ALIGN | MO_TESW)); > + return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SW)); > } > > static bool trans_sw_aqrl(DisasContext *ctx, arg_sw_aqrl *a) > { > REQUIRE_ZALASR(ctx); > - return gen_store_release(ctx, a, (MO_ALIGN | MO_TESL)); > + return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SL)); > } > > static bool trans_sd_aqrl(DisasContext *ctx, arg_sd_aqrl *a) > { > REQUIRE_64BIT(ctx); > REQUIRE_ZALASR(ctx); > - return gen_store_release(ctx, a, (MO_ALIGN | MO_TEUQ)); > + return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_UQ)); > } > diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/ins= n_trans/trans_xmips.c.inc > index 9a72f3392f1..37572563ae9 100644 > --- a/target/riscv/insn_trans/trans_xmips.c.inc > +++ b/target/riscv/insn_trans/trans_xmips.c.inc > @@ -56,11 +56,11 @@ static bool trans_ldp(DisasContext *ctx, arg_ldp *a) > TCGv addr =3D tcg_temp_new(); > > tcg_gen_addi_tl(addr, src, a->imm_y); > - tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESQ); > + tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SQ); > gen_set_gpr(ctx, a->rd, dest0); > > tcg_gen_addi_tl(addr, addr, 8); > - tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESQ); > + tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SQ); > gen_set_gpr(ctx, a->rs3, dest1); > > return true; > @@ -77,11 +77,11 @@ static bool trans_lwp(DisasContext *ctx, arg_lwp *a) > TCGv addr =3D tcg_temp_new(); > > tcg_gen_addi_tl(addr, src, a->imm_x); > - tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESL); > + tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SL); > gen_set_gpr(ctx, a->rd, dest0); > > tcg_gen_addi_tl(addr, addr, 4); > - tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESL); > + tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SL); > gen_set_gpr(ctx, a->rs3, dest1); > > return true; > @@ -99,10 +99,10 @@ static bool trans_sdp(DisasContext *ctx, arg_sdp *a) > TCGv addr =3D tcg_temp_new(); > > tcg_gen_addi_tl(addr, src, a->imm_w); > - tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TEUQ); > + tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_UQ); > > tcg_gen_addi_tl(addr, addr, 8); > - tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TEUQ); > + tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_UQ); > > return true; > } > @@ -118,10 +118,10 @@ static bool trans_swp(DisasContext *ctx, arg_swp *a= ) > TCGv addr =3D tcg_temp_new(); > > tcg_gen_addi_tl(addr, src, a->imm_v); > - tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TESL); > + tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_SL); > > tcg_gen_addi_tl(addr, addr, 4); > - tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TESL); > + tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_SL); > > return true; > } > diff --git a/target/riscv/insn_trans/trans_zilsd.c.inc b/target/riscv/ins= n_trans/trans_zilsd.c.inc > index 369c33004b6..445406cf015 100644 > --- a/target/riscv/insn_trans/trans_zilsd.c.inc > +++ b/target/riscv/insn_trans/trans_zilsd.c.inc > @@ -30,7 +30,7 @@ static bool gen_load_i64(DisasContext *ctx, arg_ld *a) > TCGv addr =3D get_address(ctx, a->rs1, a->imm); > TCGv_i64 tmp =3D tcg_temp_new_i64(); > > - tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TESQ); > + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ); > > if (a->rd =3D=3D 0) { > return true; > @@ -85,7 +85,7 @@ static bool gen_store_i64(DisasContext *ctx, arg_sd *a) > } else { > tcg_gen_concat_tl_i64(tmp, data_low, data_high); > } > - tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TESQ); > + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ); > > return true; > } > -- > 2.53.0 > >