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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::929; envelope-from=alistair23@gmail.com; helo=mail-ua1-x929.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Dec 18, 2023 at 11:00=E2=80=AFPM Daniel Henrique Barboza wrote: > > The RVA22S64 profile consists of the following: > > - all mandatory extensions of RVA22U64; > - priv spec v1.12.0; > - satp mode sv39; > - Ssccptr, a cache related named feature that we're assuming always > enable since we don't implement a cache; > - Other named features already implemented: Sstvecd, Sstvala, > Sscounterenw; > - the new Svade named feature that was recently added. > > Most of the work is already done, so this patch is enough to implement > the profile. > > After this patch, the 'rva22s64' user flag alone can be used with the > rva64i CPU to boot Linux: > > -cpu rv64i,rva22s64=3Dtrue > > This is the /proc/cpuinfo with this profile enabled: > > # cat /proc/cpuinfo > processor : 0 > hart : 0 > isa : rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_z= ihintpause_zihpm_zfhmin_zca_zcd_zba_zbb_zbs_zkt_svinval_svpbmt > mmu : sv39 > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index aa33e7a1cf..f57a9ee298 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1560,8 +1560,40 @@ static RISCVCPUProfile RVA22U64 =3D { > } > }; > > +/* > + * As with RVA22U64, RVA22S64 also defines 'named features'. > + * > + * Cache related features that we consider enabled since we don't > + * implement cache: Ssccptr > + * > + * Other named features that we already implement: Sstvecd, Sstvala, > + * Sscounterenw > + * > + * Named features that we need to enable: svade > + * > + * The remaining features/extensions comes from RVA22U64. > + */ > +static RISCVCPUProfile RVA22S64 =3D { > + .parent =3D &RVA22U64, > + .name =3D "rva22s64", > + .misa_ext =3D RVS, > + .priv_spec =3D PRIV_VERSION_1_12_0, > + .satp_mode =3D VM_1_10_SV39, > + .ext_offsets =3D { > + /* rva22s64 exts */ > + CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt), > + CPU_CFG_OFFSET(ext_svinval), > + > + /* rva22s64 named features */ > + CPU_CFG_OFFSET(svade), > + > + RISCV_PROFILE_EXT_LIST_END > + } > +}; > + > RISCVCPUProfile *riscv_profiles[] =3D { > &RVA22U64, > + &RVA22S64, > NULL, > }; > > -- > 2.43.0 > >