From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v1 2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines
Date: Mon, 12 Jul 2021 14:49:12 +1000 [thread overview]
Message-ID: <CAKmqyKMnWch1PvOaEcJDXV2kHmgRsGZN4eXp0RZ2gV4SFunKXQ@mail.gmail.com> (raw)
In-Reply-To: <aaa5d8dd-d161-684e-4204-e5bb60a2627b@linaro.org>
On Sat, Jul 10, 2021 at 1:36 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/8/21 8:30 PM, Alistair Francis wrote:
> > +typedef struct sifive_clint_callback {
> > + SiFiveCLINTState *s;
> > + int num;
> > +} sifive_clint_callback;
>
> Perhaps better to put "num", perhaps with a more descriptive name (hartid?), into
> SiFiveCLINTState itself?
The problem is that there is a single SiFiveCLINTState because there
is a single CLINT, but we want to have a timer callback for each CPU
so we need something here that is per CPU.
>
> It would avoid some amount of double-indirection, and some awkward memory allocation in
> sifive_clint_create.
>
>
> > } else if ((addr & 0x3) == 0) {
> > - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MSIP, BOOL_TO_MASK(value));
> > + if (value) {
> > + qemu_irq_raise(clint->soft_irqs[hartid]);
> > + } else {
> > + qemu_irq_lower(clint->soft_irqs[hartid]);
> > + }
>
> You should use qemu_irq_set here.
Will do!
Alistair
>
>
> r~
next prev parent reply other threads:[~2021-07-12 4:50 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-09 3:30 [PATCH v1 1/5] target/riscv: Expose interrupt pending bits as GPIO lines Alistair Francis
2021-07-09 3:30 ` [PATCH v1 2/5] hw/intc: sifive_clint: Use RISC-V CPU " Alistair Francis
2021-07-09 15:36 ` Richard Henderson
2021-07-12 4:49 ` Alistair Francis [this message]
2021-07-13 4:05 ` Anup Patel
2021-07-14 6:11 ` Alistair Francis
2021-07-22 12:15 ` Anup Patel
2021-07-09 3:31 ` [PATCH v1 3/5] hw/intc: ibex_plic: Convert the PLIC to use " Alistair Francis
2021-07-09 7:26 ` Philippe Mathieu-Daudé
2021-07-09 15:39 ` Richard Henderson
2021-07-09 3:31 ` [PATCH v1 4/5] hw/intc: sifive_plic: " Alistair Francis
2021-07-09 7:26 ` Philippe Mathieu-Daudé
2021-07-09 15:41 ` Richard Henderson
2021-07-13 4:31 ` Anup Patel
2021-07-13 5:08 ` Anup Patel
2021-07-09 3:31 ` [PATCH v1 5/5] hw/intc: ibex_timer: Convert the timer " Alistair Francis
2021-07-09 7:26 ` Philippe Mathieu-Daudé
2021-07-09 15:43 ` Richard Henderson
2021-07-09 7:25 ` [PATCH v1 1/5] target/riscv: Expose interrupt pending bits as " Philippe Mathieu-Daudé
2021-07-09 15:20 ` Richard Henderson
2021-07-10 14:40 ` Bin Meng
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